Robert F Elio

US Patent:

6856168, Feb 15, 2005

Filed:

Feb 19, 2003

Appl. No.:

10/370392

Inventors:

Kent Oertle - Phoenix AZ, US
Robert Elio - Mesa AZ, US
Duncan McFarland - Tempe AZ, US
Darrin Benzer - Chandler AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03K019/0175

US Classification:

326 81, 326 82, 326 83, 326 27

Abstract:

Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

US Patent:

7199612, Apr 3, 2007

Filed:

Jul 1, 2003

Appl. No.:

10/611585

Inventors:

Kent Oertle - Phoenix AZ, US
Robert Elio - Mesa AZ, US
Duncan McFarland - Tempe AZ, US
Darrin Benzer - Chandler AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03K 19/0175

US Classification:

326 81, 326 83, 326 26

Abstract:

Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an integrated circuit comprising an IO PAD, an output circuit coupled to at least the IO PAD and a stress circuit. The stress circuit is coupled to at least the output circuit and is adapted to limit a high voltage across the output circuit when the output circuit is enabled, thereby reducing stress on the output circuit. In one embodiment, the stress circuit comprises at least one transistor device (a p-channel device or two stacked p-channel devices, for example) and the output circuit comprises a transistor device (an n-channel device or two stacked n-channel devices).

US Patent:

7230469, Jun 12, 2007

Filed:

Sep 17, 2003

Appl. No.:

10/664379

Inventors:

Darrin Benzer - Chandler AZ, US
Robert F. Elio - Mesa AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 5/00

US Classification:

327333, 326 68, 326 81

Abstract:

Methods are disclosed for translating or shifting a voltage level of a single ended input. More specifically, the present invention provides a method of translating or shifting a voltage level that doesn't require a complementary input or an additional power supply if the complementary signal isn't available. One embodiment of the method of translating a voltage level of a single-ended input signal using at least one native transistor device having a threshold voltage less than 0V comprises outputting a first voltage level if the single ended input signal is in a first state. A second voltage level is output if the single ended input is in a second state.

US Patent:

7521965, Apr 21, 2009

Filed:

Feb 4, 2005

Appl. No.:

11/051146

Inventors:

Kent Oertle - Phoenix AZ, US
Robert Elio - Mesa AZ, US
Duncan McFarland - Tempe AZ, US
Darrin Benzer - Chandler AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03K 19/0175

US Classification:

326 83, 326 81

Abstract:

Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

US Patent:

8630071, Jan 14, 2014

Filed:

Aug 14, 2009

Appl. No.:

12/461550

Inventors:

Ramachandran Venkatasubramanian - Phoenix AZ, US
Robert Elio - Mesa AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H02H 9/00

US Classification:

361 56

Abstract:

Apparatuses and systems for dissipating ESD events are provided. In an embodiment, an integrated circuit (IC) device, includes a ground rail, a positive supply rail, a negative supply rail, a circuit block, a plurality of contact pads, and a coupling system. Each of the ground rail, positive supply rail, negative supply rail, and the circuit block are coupled to a respective contact pad of the plurality of contact pads. The contact pad coupled to the circuit block is configured to swing from a voltage of the negative rail to a voltage of the positive rail. The coupling system couples each contact pad of the plurality of contact pads to all other contact pads of the plurality of contact pads, whereby an electrostatic discharge (ESD) event between two contacts pads of the plurality of contact pads can be dissipated.

US Patent:

6650167, Nov 18, 2003

Filed:

Jun 6, 2002

Appl. No.:

10/164205

Inventors:

Darrin Benzer - Chandler AZ
Robert F. Elio - Mesa AZ

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 500

US Classification:

327333, 327427, 326 68, 326 81

Abstract:

Systems and methods are disclosed for a multi-level level shifter circuit having a single ended input and adapted to translate one or more signals from one voltage level to another. More specifically, the present invention provides a level shifter that doesnt require a complementary input or an additional power supply if the complementary signal isnt available. One embodiment of the level shifter circuit device having a single-ended input comprises at least three transistor devices. The first transistor device is coupled to at least the input and is adapted to have a threshold voltage less than 0V. The second transistor device is coupled to at least the first transistor device, while a level shifter transistor device is coupled to at least the first and second transistor devices.

US Patent:

20140126095, May 8, 2014

Filed:

Jan 13, 2014

Appl. No.:

14/153634

Inventors:

- Irvine CA, US
Robert Elio - Mesa AZ, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H02H 9/04

US Classification:

361 56

Abstract:

Apparatuses and systems for dissipating ESD events are provided. In an embodiment, an integrated circuit (IC) device, includes a ground rail, a positive supply rail, a negative supply rail, a circuit block, a plurality of contact pads, the circuit block being configured to output an output voltage via a first contact pad of the plurality of contact pads and a range of the output voltage being is between a voltage of the positive supply rail and a voltage of the negative supply rail, and a coupling system that couples the first contact pad to a second contact pad of the plurality of contact pads so as to dissipate an electrostatic discharge (ESD) event between the first and second contact pads.