Robert J Catiller

US Patent:

7031902, Apr 18, 2006

Filed:

Feb 28, 2002

Appl. No.:

10/087550

Inventors:

Robert D. Catiller - Mission Viejo CA, US

Assignee:

Western Digital Technologies, Inc. - Lake Forest CA

International Classification:

G06F 9/455

US Classification:

703 24, 703 25

Abstract:

A method for verifying the design of a disk controller circuit to be incorporated into a targeted hard disk drive system having a read/write channel and a head actuator may include steps of emulating reading and writing of data in the read/write channel based upon a model of the read/write channel, emulating a behavior of the head actuator during track seek and track following operations based upon an electromechanical model of the head actuator, providing a disk controller design base for defining integrated circuit elements comprising the disk controller circuit and providing a controller environment to support execution and debug of firmware for operating the disk controller circuit. A plurality of disk functions may be carried out at a time-scaled rate according to a script. The plurality of disk functions includes interaction of at least the read/write model, the electromechanical model, the disk controller design base and the controller environment.

US Patent:

7800856, Sep 21, 2010

Filed:

Mar 24, 2009

Appl. No.:

12/410338

Inventors:

George J. Bennett - Murrieta CA, US
Dean M. Jenkins - La Canada-Flintridge CA, US
Robert D. Catiller - Mission Viejo CA, US

Assignee:

Western Digital Technologies, Inc. - Lake Forest CA

International Classification:

G11B 21/02
G11B 5/596

US Classification:

360 75, 360 7804, 714 24, 711113

Abstract:

A disk drive is disclosed comprising a head actuated over a disk having a plurality of data tracks and a first and second set of reserved tracks, wherein the first set of reserved tracks are located at a first radial location, and the second set of reserved tracks are located at a second radial location different than the first radial location. A write command is received from a host, wherein the write command comprises user data which is stored in a cache memory. When a power failure is detected, whether the head is nearer to the first or second set of reserved tracks is determined, and then the head is positioned to the nearest of the first and second set of reserved tracks. The user data stored in the cache memory is written to the reserved tracks, and the head is unloaded onto a ramp.

US Patent:

45077320, Mar 26, 1985

Filed:

Sep 7, 1983

Appl. No.:

6/529005

Inventors:

Robert D. Catiller - Garden Grove CA
Brian K. Forbes - Huntington Beach CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 1300

US Classification:

364200

Abstract:

An I/O subsystem uses a peripheral-controller for handling data transfer operations between a host computer and a plurality of peripheral terminals. The peripheral controller is made of (a) a universal processor, which generates instructions for executing data transfer operations, and (b) an application dependent logic module which particularly adapts the instructions to each peripheral terminal connected to the system. Upon recognition of the use of addresses for slow memories, slow registers or "slow devices", control logic in the application dependent logic module controls the clocking in the universal processor to slow data transfer rates for data being placed in or removed from the "slow devices".

US Patent:

45106037, Apr 9, 1985

Filed:

Nov 25, 1983

Appl. No.:

6/555441

Inventors:

Robert D. Catiller - Garden Grove CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 1114
G06F 1124

US Classification:

371 21

Abstract:

A testing circuit is disclosed for addressing and exercising a ROM-type memory and splitting the same memory output data into two paths. One path is used to temporarily hold the memory output data for a time-interval after which it is compared, in a digital comparator, with the same memory output data on the second path. When the data on both paths compare equally, then it is known that no instability has occurred during the time-interval. If a miscompare occurs, the comparator generates an error signal.

US Patent:

44280432, Jan 24, 1984

Filed:

Aug 24, 1981

Appl. No.:

6/295587

Inventors:

Robert D. Catiller - Garden Grove CA
Craig W. Harris - El Toro CA
Ronald D. Mathews - Mission Viejo CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 304

US Classification:

364200

Abstract:

Base connection modules are used to house slide-in cards which form a Network Support Processor which executes data transfer operations for up to four main host computers. One Network Support Processor can control up to four Line Support Processors, each one of which manages up to 16 Line Adapters connected, via data communication lines, to remote terminals. The line Support Processor, via its Line Adapters, handles a wide variety of communication line disciplines but provides a common discipline to its Network Support Processor and the host computer.

US Patent:

43744168, Feb 15, 1983

Filed:

Dec 15, 1980

Appl. No.:

6/216761

Inventors:

Robert D. Catiller - Garden Grove CA
Brian K. Forbes - Huntington Beach CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 300
G06F 1300

US Classification:

364200

Abstract:

A microprocessor system having linear program sequencing and working in conjunction with an application dependent logic module tailored to handle the requirements of a variety of types of peripheral devices and wherein a microprocessor operates as a universal standard for all types of different application dependent logic modules. Means are provided for the microprocessor to access a total word from memory or to access any selected byte of a word in memory. Thus, the microprocessor and the application dependent logic module constitute a peripheral-controller which can control and monitor data transfer operations between a main host computer and a variety of peripheral devices whether such peripheral devices are "byte" oriented, such as card readers, or whether the peripheral terminal unit is "word" oriented such as magnetic tape or disk peripheral units.

US Patent:

44293895, Jan 31, 1984

Filed:

May 26, 1981

Appl. No.:

6/267041

Inventors:

Robert D. Catiller - Garden Grove CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 1122

US Classification:

371 21

Abstract:

A test pattern generator is used for generating a series of address signals such as for exercising an integrated circuit memory. Master reference clock means are used to trigger a three stage counting circuit and also a circuit array of exclusive OR gates. The outputs of the stages of the counter provide individual inputs to each of the exclusive OR gates. The array of exclusive OR gates is arranged so that each exclusive OR gate has an output line which provides one bit of information for the address signals. The combination of the outputs of the OR gates forms a parallel bus which carries the address signals to be applied to the integrated circuit memory. The circuit generates a specialized address pattern in which the original address generated is complemented, then incremented on a series of increment-complement actions so that all combinations of the row and column drivers in the integrated circuit memory are exercised.

US Patent:

44307101, Feb 7, 1984

Filed:

Aug 24, 1981

Appl. No.:

6/295586

Inventors:

Robert D. Catiller - Garden Grove CA
Craig W. Harris - El Toro CA
Ronald D. Mathews - Mission Viejo CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G06F 300
G06F 304

US Classification:

364200

Abstract:

A dual-processor, general purpose mini-computer which is programmed as a front-end data communications processor and is called a Network Support Processor. Data transfer commands received from a main host computer are executed and result messages are returned to the main host computer by the Network Support Processor. A base connection module providing slide-in connector cards houses and supports circuit cards which make up the Network Support Processor. These cards include a master controller which includes a master processor card, a master memory control card and an Interface Card which connects to a main host computer and to one or more line communications processors, each of which may handle up to 16 data communications lines. A slave controller likewise includes a slave processor circuit card, and a slave memory control circuit card. A series of slide-in memory cards forming a shared memory storage means connect to both the master and the slave memory control circuit cards.