Robert A Ayrapetian

US Patent:

7499464, Mar 3, 2009

Filed:

Apr 6, 2006

Appl. No.:

11/400367

Inventors:

Robert Ayrapetian - Morgan Hill CA, US
Edward Ayrapetian - Morgan Hill CA, US
Serob Douvalian - Morgan Hill CA, US

International Classification:

H04L 12/28

US Classification:

370419, 370412, 370428, 710 52

Abstract:

A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.

US Patent:

8077646, Dec 13, 2011

Filed:

Jul 3, 2008

Appl. No.:

12/167911

Inventors:

Raphael Cendrillon - Kennedy Town, HK
Robert Ayrapetian - Morgan Hill CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H04B 7/00

US Classification:

370310

Abstract:

An equalization method and apparatus for a communication system having a first transceiver device that communicates with each of a plurality of second transceiver devices receives a data transmission over a subset of frequency sub-carriers allotted to each second transceiver device. The communication channel between first transceiver device and the plurality of second transceiver devices is partitioned in a plurality of frequency sub-carriers of which the frequency sub-carriers allotted to a second transceiver device is a subset. The data transmission is transformed from a time-domain transmission to a frequency domain transmission. An equalization filter is applied separately to each of the frequency sub-carriers within the subset of frequency sub-carriers.

US Patent:

20070121660, May 31, 2007

Filed:

Nov 6, 2006

Appl. No.:

11/593807

Inventors:

Robert Ayrapetian - Morgan Hill CA, US
Serob Douvalian - Daly City CA, US

International Classification:

H04L 12/56

US Classification:

370411000

Abstract:

A network switch is provided that includes a bank of input switches configured to receive variable length data packets; a bank of central switches configured to receive packets from the input switches in a distributed manner; and a bank of output switches configured to receive and output variable length packets from the bank of central switches.

US Patent:

20070140260, Jun 21, 2007

Filed:

Nov 6, 2006

Appl. No.:

11/593858

Inventors:

Simon Duxbury - San Francisco CA, US
Robert Ayrapetian - Morgan Hill CA, US
Serob Douvalian - Daly City CA, US

International Classification:

H04L 12/56

US Classification:

370395410

Abstract:

An improved string switch architecture is provided having a partial shared memory. The string switch includes a plurality of input ports configured to classify incoming packets, wherein the destination output port and priority is determined at classification; a plurality of output ports, each having a string bank of memory units that compose the aggregate output queue memory for each port; a write manager configured to receive write requests and to write each packet directly to the appropriate memory location within each output port; where each output port includes an assignment block configured to receive packets originating from each input port; and a read manager configured to read data from the plurality of output ports. The write manager may be configured to write packet data received in a round robin fashion, which may be independent from the packet protocol.

US Patent:

20100034208, Feb 11, 2010

Filed:

Jan 20, 2009

Appl. No.:

12/356185

Inventors:

Robert Ayrapetian - Morgan Hill CA, US
Edward Ayrapetian - Morgan Hill CA, US
Serob Douvalian - Daly City CA, US

International Classification:

H04L 12/56

US Classification:

370401

Abstract:

A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.

US Patent:

20100316102, Dec 16, 2010

Filed:

Jun 15, 2010

Appl. No.:

12/802884

Inventors:

Robert Ayrapetian - Morgan Hill CA, US
Qasem Aldrubi - Fremont CA, US
Hossein Dehghan-Fard - Danville CA, US
Christopher Chow - Redwood City CA, US

Assignee:

IKANOS COMMUNICATIONS, Inc. - Fremont CA

International Classification:

H04B 1/38
H04L 25/00

US Classification:

375222, 375227, 375371

Abstract:

A multi-tone transceiver including: a transform component, a tone selector, an error detector, an aggregator and an oscillator. The transform component transforms received communications from the time domain to the frequency domain. The tone selector selects a sub-set of the received tones which exhibit an elevated signal-to-noise ratio (SNR) as a clock recovery tone set (CRTS) and drops and add tones to the CRTS as required by changes in the SNR of the individual tones. The error detector detects phase errors in each received tone of the CRTS. The aggregator calculates an average aggregate phase error from all tones in the CRTS. The oscillator controls clocking of the transceiver. The oscillator is responsive to the average aggregate phase error to adjust a clock phase in a direction which reduces a phase error with a clock on the opposing transceiver.

US Patent:

7076002, Jul 11, 2006

Filed:

Apr 5, 2002

Appl. No.:

10/117823

Inventors:

Fernando Ramirez-Mireles - Walnut Creek CA, US
Robert Ayrapetian - Morgan Hill CA, US
Dale Smith - Fremont CA, US
Max Chien - Menlo Park CA, US
Sam Heidari - Menlo Park CA, US

Assignee:

Ikanos Communication, Inc. - Fremont CA

International Classification:

H04L 27/14
H04L 7/00
H04J 3/06
H04J 3/12

US Classification:

375316, 375355, 370503, 370523

Abstract:

The apparatus for symbol boundary synchronization in one embodiment includes on the receive path of a multi-tone modem a window synchronizer, a converter and a symbol boundary component. The window synchronizer obtains windowed portions of the received datastream which includes symbols each expressed with a corresponding set of tones in a time domain. The windowed portions obtained in the training phase exhibit varying degrees of misalignment with the corresponding symbol boundaries. The window synchronizer is responsive to an alignment signal to obtain succeeding windowed portions of the incoming datastream aligned with the corresponding symbol boundaries therein. The converter couples to the window synchronizer to convert the set of tones from each windowed portion from the time domain to a frequency domain. The symbol boundary module couples to the converter to evaluate a phasor angle characteristic of selected tones from each windowed portion converted by the converter and to convert the phasor angle characteristic of the selected tones from a selected one of the windowed portions to the alignment signal to align the window synchronizer with the symbol boundaries in the received datastream. In an alternate embodiment of the invention the symbol boundary component couples to the window synchronizer to correlate sign values of the selected tones with a reference set and to output the alignment signal identifying the corresponding windowed portion which exhibits maximum correlation with the reference set to align the window synchronizer.