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Rien C Gahlsdorf

age ~51

from Bedford, NH

Also known as:
  • Rien Christopher Gahlsdorf
  • Rhio R Gahlsdorf
  • Rein C Gahlsdorf
  • Rhio Reigh Galsdorf
  • Rhio R Galsdorf
Phone and address:
295 Liberty Hill Rd, Manchester, NH 03110
603 488-2066

Rien Gahlsdorf Phones & Addresses

  • 295 Liberty Hill Rd, Bedford, NH 03110 • 603 488-2066
  • Merrimack, NH
  • 6 Terry St, Nashua, NH 03064
  • 4 Silver Dr, Nashua, NH 03060
  • 48 Williams St, Nashua, NH 03060
  • 4781 Teralee Ln, Eugene, OR 97402
  • Stockton, CA
  • Hudson, NH
  • 295 Liberty Hill Rd, Bedford, NH 03110

Us Patents

  • Activity Detector Circuit

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  • US Patent:
    20030173999, Sep 18, 2003
  • Filed:
    Mar 17, 2003
  • Appl. No.:
    10/389839
  • Inventors:
    Rien Gahlsdorf - Nashua NH, US
    Fouad Kiamilev - Hockessin DE, US
  • International Classification:
    H03K005/153
  • US Classification:
    327/077000
  • Abstract:
    An activity detection system for use with a signal having a high value and a low value has a differential amplifier, a filter and a comparator configured to compare a signal to a threshold value and determine if the threshold value is above the signal, below the signal or in between the high and low values of the signal.
  • On Chip Ac Coupled Circuit

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  • US Patent:
    20030184381, Oct 2, 2003
  • Filed:
    Mar 17, 2003
  • Appl. No.:
    10/390101
  • Inventors:
    Theodore Wyman - Mont Vernon NH, US
    Robert Martin - Orlando FL, US
    Rien Gahlsdorf - Nashua NH, US
  • International Classification:
    H03F003/16
  • US Classification:
    330/277000
  • Abstract:
    An alternating current coupling circuit is made up of a chip located within a chain of differential amplifier circuits having thereon a) a filter circuit, having an output, the filter circuit being constructed to filter out a direct current component in a low swing alternating current (AC) signal; and b) a current amplifier circuit, connected to the output of the filter, that amplifies a current associated with the AC signal.
  • Eye Safety Shutdown

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  • US Patent:
    20030002109, Jan 2, 2003
  • Filed:
    Jun 29, 2001
  • Appl. No.:
    09/897165
  • Inventors:
    Jim Hochberg - Bedford NH, US
    Rien Gahlsdorf - Nashua NH, US
    Tim Ireland - Amherst NH, US
    Ted Wyman - Mount Vernon NH, US
  • International Classification:
    H04B010/08
    H04B010/00
  • US Classification:
    359/152000, 359/110000
  • Abstract:
    A method of minimizing a risk of damage to human tissue, caused by an exposure to an amount of laser radiation in excess of a maximum permissible exposure level performed in an optical transceiver having at least two photodetectors and at least two laser transmitters. The method involves monitoring at least one of the photodetectors for receipt of an optical signal; determining if a received optical signal satisfies at least one expected activity criterion; and, if the received optical signal does not satisfy the at least one expected activity criterion, determining that an eye safety fault condition exists and causing a shut down of at least one of the at least two laser transmitters. An optical transceiver with multiple optical devices includes a transmit channel; a receiver channel; an eye safety channel; and a controller, coupled to the transmit channel and eye safety channel. The controller is configured to receive information based upon a monitoring of the eye safety channel and shut down the transmit channel when the information indicates that an eye safety fault has occurred.
  • Mos Capacitors Flow Type Devices And Methods Of Forming The Same

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  • US Patent:
    20160293778, Oct 6, 2016
  • Filed:
    Mar 30, 2016
  • Appl. No.:
    15/085788
  • Inventors:
    - Tokyo, JP
    Rien Gahlsdorf - Bedford NH, US
  • International Classification:
    H01L 29/94
    G05F 3/24
    H03H 19/00
    H01L 27/08
    H01L 29/66
    G05F 3/20
    H01L 27/12
  • Abstract:
    A capacitor structure is described. The capacitor structure includes a substrate; a source/drain region formed in the substrate to form an active area, the active area having an active area width; and at least two gates formed above the substrate. The at least two gates having a gate width. The gate width is configured to be less than the active area width. And, the at least two gates are formed such that the source/drain region is between the two gates to form at least one channel between the two gates.
  • Mos Capacitors Structures For Variable Capacitor Arrays And Methods Of Forming The Same

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  • US Patent:
    20160293779, Oct 6, 2016
  • Filed:
    Mar 30, 2016
  • Appl. No.:
    15/085834
  • Inventors:
    - Tokyo, JP
    Rien Gahlsdorf - Bedford NH, US
  • International Classification:
    H01L 29/94
    H01L 27/08
    H01L 29/66
    G05F 3/24
    H01L 29/423
    H01L 27/02
    H03H 19/00
    G05F 3/20
    H01L 27/12
    H01L 29/08
  • Abstract:
    A capacitor structure is described. A capacitor structure including a substrate; a source/drain region formed in the substrate to form an active area having an active area width; and a plurality of gates formed above the substrate. The source/drain region having a reflection symmetry. Each of the plurality of gates having a gate width. The gate width is configured to be less than said active area width. And, the plurality of gates are formed to have reflection symmetry.
  • Mos Capacitors For Variable Capacitor Arrays And Methods Of Forming The Same

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  • US Patent:
    20160294366, Oct 6, 2016
  • Filed:
    Mar 30, 2016
  • Appl. No.:
    15/085572
  • Inventors:
    - Tokyo, JP
    Rien Gahlsdorf - Bedford NH, US
  • International Classification:
    H03H 19/00
    G05F 3/20
    G05F 3/24
    H01L 49/02
  • Abstract:
    A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions formed in the substrate, and a plurality of gates formed above the substrate. The plurality of gates formed above the substrate such that each of the plurality of gates is formed between each pair of source/drain regions of the plurality of source/drain regions to form a channel between each pair of source/drain regions.
  • Mos Capacitors With Interleaved Fingers And Methods Of Forming The Same

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  • US Patent:
    20160294367, Oct 6, 2016
  • Filed:
    Mar 30, 2016
  • Appl. No.:
    15/085669
  • Inventors:
    - Tokyo, JP
    Rien Gahlsdorf - Bedford NH, US
  • International Classification:
    H03H 19/00
    G05F 3/20
    H01L 49/02
  • Abstract:
    A capacitor structure is described. The capacitor structure includes a substrate; a plurality of source/drain regions formed in said substrate to form an active area, the active area having an active area width; and a first and a second plurality of gates formed above the substrate. Each gate of the first and second plurality of gates having a gate width. The gate width is configured to be less than the active area width and each gate of the first and second plurality of gates is formed between a pair of source/drain regions of the plurality of source/drain regions such that the first plurality of gates interleave with the second plurality of gates.
  • Mos Capacitors With Head-To-Head Fingers And Methods Of Forming The Same

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  • US Patent:
    20160294368, Oct 6, 2016
  • Filed:
    Mar 30, 2016
  • Appl. No.:
    15/085720
  • Inventors:
    - Tokyo, JP
    Rien Gahlsdorf - Bedford NH, US
  • International Classification:
    H03H 19/00
    G05F 3/20
    G05F 3/24
    H01L 49/02
  • Abstract:
    A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions, a first plurality gates, and a second plurality of gates. The plurality of source/drain regions is formed in the substrate. The first and second plurality of gates is formed above the substrate. Each gate of the first and second plurality of gates has a gate width. The gate widths are configured to be less than an active area width and each gate of the first and second plurality of gates is formed between a pair of the source/drain regions of the plurality of source/drain regions. And, each gate of the first plurality of gates is configured to be in line with a corresponding gate of the second plurality of gates to form a head-to-head gate configuration.

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