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Richard Win Thaik

age ~56

from San Jose, CA

Also known as:
  • Richard W Thaik
  • Richard Win Te Thaik
  • Richard Min Thaik
  • Richard Win Thaik Revocabl
  • Richard Win Thaik Revocable
  • Dick W Thaik
  • Rick W Thaik
  • Richard W Thair
  • Rich Thaik
  • Richard C
Phone and address:
2773 Scott St, San Jose, CA 95128
408 896-3843

Richard Thaik Phones & Addresses

  • 2773 Scott St, San Jose, CA 95128 • 408 896-3843
  • Wescosville, PA
  • Torrance, CA
  • Franklin, IN
  • W Lafayette, IN
  • W Lafayette, IN
  • 1566 Cleo Springs Dr, San Jose, CA 95131 • 408 896-3843

Work

  • Position:
    Production Occupations

Education

  • Degree:
    Graduate or professional degree

Us Patents

  • Asynchronous Processor Access To A Switch Table In A Network With Isochronous Capability

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  • US Patent:
    RE39216, Aug 1, 2006
  • Filed:
    Jan 14, 1999
  • Appl. No.:
    09/231855
  • Inventors:
    Debra J. Worsley - San Jose CA, US
    Michael T. Werstlein - Portland OR, US
    Richard W Thaik - San Jose CA, US
  • Assignee:
    Negotiated Data Solutions LLC - Chicago IL
  • International Classification:
    H04L 12/42
  • US Classification:
    37039553, 370513, 709242
  • Abstract:
    A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. Switching of data is handled using switching tables. The tables can be updated by a processor. Updates can be performed asynchronously so that the processor does not have to wait until the switch tables are in an unused updatable state before outputting the update information. An efficient encoding scheme permits transmission of both isochronous and non-isochronous data over existing media, such as twisted pair, without degrading bandwidth previously achieved for non-isochronous data over the same media, such as using an Ethernet system. The arriving data is de-multiplexed at the hub into separate channels for handling the separate streams by appropriate hardware.
  • Data Communication Network With Transfer Port, Cascade Port And/Or Frame Synchronizing Signal

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  • US Patent:
    RE39395, Nov 14, 2006
  • Filed:
    Oct 15, 1998
  • Appl. No.:
    09/173582
  • Inventors:
    Geetha N. K. Rangan - Los Altos Hills CA, US
    Debra J. Worsley - San Jose CA, US
    Richard Thaik - San Jose CA, US
    Brian C. Edem - Saratoga CA, US
  • Assignee:
    Negotiated Data Solutions LLC - Chicago IL
  • International Classification:
    H04J 3/14
  • US Classification:
    370366, 370352, 370426
  • Abstract:
    A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. An efficient encoding scheme permits transmission of both isochronous and non-isochronous data over existing media, such as twisted pair, without degrading bandwidth previously achieved for non-isochronous data over the same media, such as using an ethernet system. Bandwidth available for a particular isochronous source/sink is selectable and sustainable with a predefined granularity. The arriving data is de-multiplexed at the hub into separate channels for handling the separate streams by appropriate hardware. Preferably, the present invention can be implemented in a fashion that is transparent to already-installed media access controllers. Preferably, some components of the system can detect the frame-transmission capability of other components and, if such capability is lacking, can fall back to a mode compliant with existing capabilities.
  • Software Hint To Specify The Preferred Branch Prediction To Use For A Branch Instruction

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  • US Patent:
    7673122, Mar 2, 2010
  • Filed:
    Dec 16, 2005
  • Appl. No.:
    11/306000
  • Inventors:
    Seungyoon Peter Song - East Palo Alto CA, US
    John Gregory Favor - Scotts Valley CA, US
    Richard W. Thaik - San Jose CA, US
  • Assignee:
    Sun Microsystems, Inc. - Santa Clara CA
  • International Classification:
    G06F 9/00
  • US Classification:
    712239, 712240
  • Abstract:
    Software hints embedded in branch instructions direct selection of one of a plurality of branch predictors to use when processing the branch instructions, leading to improved branch prediction (i. e. fewer mis-predictions) over conventional schemes. A software agent assembles branch instructions having associated respective branch predictor control fields compatible with a branch predictor selector and a plurality of branch predictors. Each branch predictor control field is used to perform branch predictor selection, branch predictor control, or both. Branch predictor selection enables selective branch prediction according to an appropriate one of the branch predictors as determined by the software agent by examining context surrounding the branch instruction. Branch predictor control enables control of operation of one or more of the branch predictors. For example, a history-based branch predictor may be instructed to provide branch prediction according to a history-depth specified by the branch predictor control.
  • Maintaining Memory Coherency With A Trace Cache

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  • US Patent:
    7747822, Jun 29, 2010
  • Filed:
    Oct 31, 2006
  • Appl. No.:
    11/591024
  • Inventors:
    John G. Favor - Santa Clara CA, US
    Richard W. Thaik - Santa Clara CA, US
  • Assignee:
    Oracle America Inc. - Redwood City CA
  • International Classification:
    G06F 12/08
  • US Classification:
    711125, 711118, 711141, 711144
  • Abstract:
    A method and system for maintaining memory coherence in a trace cache is disclosed. The method and system comprises monitoring a plurality of entries in a trace cache. The method and system includes selectively invalidating at least one trace cache entry based upon detection of a modification of the at least one trace cache entry. If modifications are detected, then corresponding trace cache entries are selectively invalidated (rather than invalidating the entire trace cache). Thus trace cache coherency is maintained with respect to memory in a performance and power-efficient manner. The monitoring further accounts for situations where more than one trace cache entry is dependent on a single cache line, such that modifications to the single cache line result in invalidations of a plurality of trace cache entries.
  • Graceful Degradation In A Trace-Based Processor

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  • US Patent:
    7783863, Aug 24, 2010
  • Filed:
    Oct 24, 2007
  • Appl. No.:
    11/923638
  • Inventors:
    Christopher Patrick Nelson - Santa Clara CA, US
    John Gregory Favor - Scotts Valley CA, US
    Richard Win Thaik - San Jose CA, US
    Matthew William Ashcraft - Belmont CA, US
  • Assignee:
    Oracle America, Inc. - Redwood City CA
  • International Classification:
    G06F 9/00
  • US Classification:
    712220, 712227, 712216, 712207
  • Abstract:
    A method of handling a trace to be aborted includes receiving an indication of a trace to be aborted and an indication of an abort reason corresponding to an execution of the trace to be aborted. The trace to be aborted has a trace type associated therewith and includes a sequence of the operations, and represents a sequence of at least two of the instructions. The method further includes identifying a corrective action based at least in part on the type of the trace to be aborted and on the abort reason, not taking into account a correspondence between the at least one operation that caused the execution to be aborted and the at least one instruction that the at least one operation at least in part represents. A next trace and its trace type is determined for execution, where the determining is based on the trace to be aborted and on the corrective action.
  • Promoting And Appending Traces In An Instruction Processing Circuit Based Upon A Bias Value

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  • US Patent:
    7814298, Oct 12, 2010
  • Filed:
    Nov 16, 2007
  • Appl. No.:
    11/941883
  • Inventors:
    Richard Thaik - Santa Clara CA, US
    John Gregory Favor - Santa Clara CA, US
    Joseph Rowlands - Santa Clara CA, US
    Leonard Eric Shar - Santa Clara CA, US
    Matthew Ashcraft - Belmont CA, US
  • Assignee:
    Oracle America, Inc. - Redwood City CA
  • International Classification:
    G06F 9/30
  • US Classification:
    712207, 712235
  • Abstract:
    A method, system and computer program product for promoting a trace in an instruction processing circuit is disclosed. They comprise determining if a current trace is promotable and determining if a next trace is appendable to the current trace. They include promoting the current trace and the next trace if the current trace is promotable and the next trace is appendable.
  • Flag Optimization Of A Trace

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  • US Patent:
    7849292, Dec 7, 2010
  • Filed:
    Nov 16, 2007
  • Appl. No.:
    11/941900
  • Inventors:
    Matthew William Ashcraft - Belmont CA, US
    John Gregory Favor - Scotts Valley CA, US
    Christopher Patrick Nelson - Santa Clara CA, US
    Ivan Pavle Radivojevic - San Francisco CA, US
    Joseph Byron Rowlands - Santa Clara CA, US
    Richard Win Thaik - San Jose CA, US
  • Assignee:
    Oracle America, Inc. - Redwood City CA
  • International Classification:
    G06F 9/00
  • US Classification:
    712220
  • Abstract:
    A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include locating an operation, if any, that is next within the sequence of operations and setting a current operation to be that operation. The current operation is processed as follows: a) de-activating, if not already de-activated, a consumed indicator associated with the current operation; and b) when the current operation is of the producer type, then activating, if not already activated, a producer indicator associated with the current operation, and locating a first set of operations, if any, that i) are earlier in the sequence of operations than the current operation, ii) have their associated producer indicator activated, and iii) have their associated consumed indicator de-activated, and then de-activating the producer indicator associated with each operation in the first set. When the current operation is of the consumer type, then locating a second set of operations, if any, that are earlier in the sequence of operations than the current operation, and then activating, if not already activated, the consumed indicator associated with each operation in the second set.
  • Abort Prioritization In A Trace-Based Processor

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  • US Patent:
    7870369, Jan 11, 2011
  • Filed:
    Oct 24, 2007
  • Appl. No.:
    11/923640
  • Inventors:
    Christopher Patrick Nelson - Santa Clara CA, US
    John Gregory Favor - Scotts Valley CA, US
    Richard Win Thaik - San Jose CA, US
  • Assignee:
    Oracle America, Inc. - Redwood City CA
  • International Classification:
    G06F 9/00
  • US Classification:
    712220, 712207, 712216
  • Abstract:
    A method of determining a reason for a trace to be aborted includes receiving at least two incoming indications of occurrences of abort triggers stemming from the execution of at least two of the operations that are different from each other, where each of the abort triggers has an associated abort priority level, and where the trace represents multiple instructions. The method further includes prioritizing among the abort triggers for the trace based on the abort priority level of each abort trigger, where the prioritizing does not take into account a correspondence between operations and instructions and where the prioritizing selects as a pending abort reason one or more of the abort triggers that have the same abort priority level, and where that abort priority level is the highest among the abort priority levels of the abort triggers for the trace.

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