Richard P Rouse

Author:

Richard W. Rouse

ISBN #:

0806651121

Author:

Richard H. Rouse

ISBN #:

0268006229

Author:

Richard H. Rouse

ISBN #:

0268006237

Author:

Richard H. Rouse

ISBN #:

0520014561

Author:

Richard H. Rouse

ISBN #:

0520096444

Author:

Richard H. Rouse

ISBN #:

0520096878

Author:

Richard H. Rouse

ISBN #:

0712300740

Author:

Richard H. Rouse

ISBN #:

0873280822

US Patent:

6475868, Nov 5, 2002

Filed:

Aug 17, 2000

Appl. No.:

09/640082

Inventors:

Ming Yin Hao - Sunnyvale CA
Asim Selcuk - Cupertino CA
Richard P. Rouse - San Francisco CA
Emi Ishida - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

438301, 438528

Abstract:

Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.

US Patent:

6531347, Mar 11, 2003

Filed:

Feb 6, 2001

Appl. No.:

09/776713

Inventors:

Carl R. Huster - Sunnyvale CA
Judy An - San Jose CA
Richard P. Rouse - San Francisco CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2184

US Classification:

438164, 438163, 438300, 438301

Abstract:

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming source and drain regions that are recessed a prescribed depth below the main surface of the semiconductor substrate. Sidewall spacers and a silicide layer are subsequently formed on the gate electrode stack. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

US Patent:

7064043, Jun 20, 2006

Filed:

Dec 9, 2004

Appl. No.:

11/008007

Inventors:

Richard P. Rouse - Santa Clara CA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/20
H01L 21/8242

US Classification:

438396, 438393, 438250, 438239

Abstract:

A technique for forming a MOS capacitor () that can be utilized as a decoupling capacitor is disclosed. The MOS capacitor () is formed separately from the particular circuit device () that it is to service. As such, the capacitor () and its fabrication process can be optimized in terms of efficiency, etc. The capacitor () is fabricated with conductive contacts () that allow it to be fused to the device () via conductive pads () of the device (). As such, the capacitor () and device () can be packaged together and valuable semiconductor real estate can be conserved as the capacitor () is not formed out of the same substrate as the device (). The capacitor () further includes deep contacts () whereon bond pads () can be formed that allow electrical connection of the capacitor () and device () to the outside world.

US Patent:

7673260, Mar 2, 2010

Filed:

Oct 24, 2006

Appl. No.:

11/586827

Inventors:

Haizhou Chen - Santa Clara CA, US
Li-Fu Chang - Santa Clara CA, US
Richard Rouse - Santa Clara CA, US
Nishath Verghese - Santa Clara CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4

Abstract:

DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

US Patent:

8225248, Jul 17, 2012

Filed:

Oct 24, 2006

Appl. No.:

11/588095

Inventors:

Haizhou Chen - Santa Clara CA, US
Li-Fu Chang - Santa Clara CA, US
Richard Rouse - Santa Clara CA, US
Nishath Verghese - Santa Clara CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716106, 716111, 716112, 716113, 716132, 716136, 716139, 716 51

Abstract:

DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

US Patent:

20100275170, Oct 28, 2010

Filed:

Apr 27, 2010

Appl. No.:

12/768139

Inventors:

Narayanasamy Subramanian - San Jose CA, US
Richard P. Rouse - Sunnyvale CA, US
Ziding Yue - Campbell CA, US

Assignee:

MOSYS, INC. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 3

Abstract:

A computer-based method of converting an analog integrated circuit design from a source technology to a target technology, by providing a computer readable source schematic file and a computer readable source layout file for the analog integrated circuit design in the source technology, providing a computer readable technology transfer file that includes conversion tables between properties of the source technology and properties of the target technology, converting the source schematic file in the source technology to a target schematic file in the target technology with the computer using the technology transfer file, and converting the source layout file in the source technology to a target layout file in the target technology with the computer using the technology transfer file.

US Patent:

62423290, Jun 5, 2001

Filed:

Feb 3, 1999

Appl. No.:

9/243875

Inventors:

Carl Robert Huster - Sunnyvale CA
Concetta Riccobene - Mountain View CA
Richard Rouse - San Francisco CA
Donald L. Wollesen - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21425

US Classification:

438531

Abstract:

A method for manufacturing a field effect transistor (100) includes steps of forming a gate stack (102) on the surface (114) of a semiconductor substrate (108), and defining source/drain regions (104, 106) on either side of the gate stack and a channel region (130) under the gate stack. The channel region has one end (132) proximate a first source/drain region and another end (134) proximate a second source/drain region. The method further includes forming a masking layer (174) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

US Patent:

62251708, May 1, 2001

Filed:

Oct 28, 1999

Appl. No.:

9/428481

Inventors:

Effiong Ibok - Sunnyvale CA
Richard P. Rouse - San Francisco CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336
H01L 213205

US Classification:

438291

Abstract:

In order to form a self-aligned damascene gate with an attendant contact or contacts, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annealed. This dielectric layer is polished for planarity, a combined gate and contact mask is used to pattern the dielectric, and the interlayer dielectric is etched and the resist is stripped. The gate dielectric is deposited and polysilicon is then deposited over the dielectric and doped by implantation and then annealed. This polysilicon layer is polished to the dielectric level. The wafer is then masked to cover the gate and the polysilicon is anisotropically etched off in the contact areas. The exposed polysilicon at the gate site and the silicon exposed at the contact site are then salicided.