Rezaur R Khan

US Patent:

7462933, Dec 9, 2008

Filed:

Jun 27, 2006

Appl. No.:

11/475118

Inventors:

Sam Ziqun Zhao - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/48
H01L 23/52
H01L 23/10

US Classification:

257713, 257706, 257784, 257780, 257E23101

Abstract:

Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface coupled to the surface of the substrate. An area of the surface of the stiffener can be greater than, equal to, or less than an area of the surface of the substrate. A thermal connector is coupled to the surface of the stiffener through the opening. A surface of the thermal connector is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. The thermal connector can have a height such that the thermal connector extends into a cavity formed in a surface of the PCB when the BGA package is mounted to the PCB. Alternatively, the stiffener and thermal connector may be combined into a single piece stiffener, wherein the stiffener has a protruding portion. The protruding portion extends through the opening when the stiffener is coupled to the substrate, and is capable of attachment to the PCB.

US Patent:

7566590, Jul 28, 2009

Filed:

Jan 9, 2007

Appl. No.:

11/621352

Inventors:

Chong Hua Zhong - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 21/44
H01L 21/48
H01L 21/50

US Classification:

438119, 438118, 438122, 257707, 257712

Abstract:

An apparatus and method for a low voltage drop and thermally enhanced integrated circuit (IC) package are described. A substantially planar substrate having a plurality of contact pads on a first surface is electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate. An IC die having a first surface is mounted to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. A heat sink assembly is coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The heat sink assembly can also provide an electrical path from the IC die to the first surface of the substrate. The heat sink assembly may have one or two heat sink elements to provide thermal and/or electrical connectivity between the IC die and the substrate.

US Patent:

7579217, Aug 25, 2009

Filed:

Aug 25, 2006

Appl. No.:

11/509715

Inventors:

Sam Ziqun Zhao - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 21/44
H01L 21/48

US Classification:

438122, 438125, 438617, 257E23101

Abstract:

An electrically and thermally enhanced die-up tape substrate ball grid array (BGA) package and die-up plastic substrate BGA package are described. A substrate that has a first surface and a second surface is provided. The stiffener has a first surface and a second surface. The second stiffener surface is attached to the first substrate surface. An IC die has a first surface and a second surface. The first IC die surface is mounted to the first stiffener surface. A plurality of solder balls is attached to the second substrate surface. In one aspect, a heat spreader is mounted to the second IC die surface. In another aspect, the stiffener is coupled to ground to act as a ground plane. In another aspect, the substrate has a window opening that exposes a portion of the second stiffener surface. The exposed portion of the second stiffener surface is configured to be coupled to a printed circuit board (PCB). In another aspect, a metal ring is attached to the first stiffener surface.

US Patent:

7618849, Nov 17, 2009

Filed:

Oct 22, 2007

Appl. No.:

11/876467

Inventors:

Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Ken Jian Ming Wang - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/495

US Classification:

438127, 257675, 438122

Abstract:

Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner.

US Patent:

7714453, May 11, 2010

Filed:

Jan 11, 2007

Appl. No.:

11/652007

Inventors:

Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Sam Ziqun Zhao - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/28
H01L 29/40
H01L 29/06
H01L 23/02
H01L 23/34
H01L 23/48
H01L 23/52

US Classification:

257787, 257621, 257622, 257623, 257678, 257685, 257686, 257723, 257737, 257738, 257777, 257778, 257E2302, 257E23021, 257E23085, 257E23123, 257E23128

Abstract:

Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that are electrically coupled to a plurality of electrically conductive features on the second surface. The plurality of conductive elements is formed on the first surface of the substrate. The IC die is located on the first surface of the substrate. The encapsulating material encapsulates the IC die and a portion of each element of the plurality of conductive elements.

US Patent:

7808087, Oct 5, 2010

Filed:

Sep 27, 2006

Appl. No.:

11/527573

Inventors:

Sam Ziqun Zhao - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/495

US Classification:

257670, 257E23054

Abstract:

Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes first and second caps defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. Planar rim portions of the first and second caps that surround the cavity are coupled to the leadframe. The first and second caps and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

US Patent:

7872335, Jan 18, 2011

Filed:

Nov 30, 2007

Appl. No.:

11/987452

Inventors:

Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Ken Jian Ming Wang - San Francisco CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/495
H01L 23/02

US Classification:

257666, 257686, 257723, 257E23051

Abstract:

Methods and apparatus for integrated circuit (IC) packages with improved thermal performance and input/output capabilities are described. An integrated circuit (IC) package includes a leadframe, an IC die, a substrate having opposing first and second surfaces, a first wirebond, and a second wirebond. The leadframe includes a die attach pad having opposing first and second surfaces and a plurality of leads that emanate in an outward direction from the die attach pad. The IC die is coupled to the first surface of the die attach pad. The substrate is coupled to the die attach pad. Contact pads on the first surface of the substrate are electrically connected to bond fingers on the second surface of the substrate. The first wirebond couples a first bond pad on a first surface of the IC die to a bond finger on the second surface of the substrate. The second wirebond couples a second bond pad on the first surface of the IC die to a lead of the plurality of leads.

US Patent:

8039949, Oct 18, 2011

Filed:

Nov 16, 2009

Appl. No.:

12/619385

Inventors:

Sam Ziqun Zhao - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Edward Law - Tracy CA, US
Marc Papageorge - Pleasanton CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/48

US Classification:

257701, 257702, 257703, 257E23003, 257E23194

Abstract:

Electrically and thermally enhanced die-up ball grid array (BGA) packages are described. A BGA package includes a stiffener, substrate, a silicon die, and solder balls. The die is mounted to the top of the stiffener. The stiffener is mounted to the top of the substrate. A plurality of solder balls are attached to the bottom surface of the substrate. A top surface of the stiffener may be patterned. A second stiffener may be attached to the first stiffener. The substrate may include one, two, four, or other number of metal layers. Conductive vias through a dielectric layer of the substrate may couple the stiffener to solder balls. An opening may be formed through the substrate, exposing a portion of the stiffener. The stiffener may have a down-set portion. A heat slug may be attached to the exposed portion of the stiffener.