Raymond Lee Warner

US Patent:

20010002650, Jun 7, 2001

Filed:

Nov 23, 1998

Appl. No.:

09/198220

Inventors:

RAYMOND M. WARNER - EDINA MN, US
JOHN E. MACCRISKEN - WATSONVILLE CA, US

International Classification:

C23C014/34

US Classification:

204/298040, 204/298020, 204/298060, 204/298110

Abstract:

Three technologies are brought together to realize monocrystalline three-dimensional (3-D) integrated circuits. They are silicon sputter epitaxy, which permits fast growth at low temperatures, and can be switched instantaneously to a material-removal mode by a bias change; (2) real-time pattern generation, which uses a Digital Micromirror Device, or one of similar properties, to create a beam of energetic radiation that is patterned on a pixel-by-pixel basis; and (3) flash diffusion, which focuses the patterned beam on a silicon surface, causing localized heating, and localized dopant diffusion from a heavily doped region at the surface into the underlying region. By removing the heavily doped layer, one is left with a 2-D doping pattern, and by creating additional 2-D patterns on top of it through process repetition, one arrives at a buried 3-D doping pattern. A preferred configuration places projector barrel and sample in fixed positions inside the sputtering chamber and places a ring of targets around the barrel, each “aimed at” the sample, with two or more targets of a given kind symmetrically positioned in the ring. A metal such as cobalt or nickel will be substituted for the heavily doped layer that is subjected to flash diffusion, thus driving in the metal and creating silicide patterns of enhanced conductivity for use as circuit conductors. Patterned radiation from lasers, flash tubes, or mercury arcs will be used to give atoms on the sample surface extra energy, thus altering sputter-deposition rates and ion-milling rates. This differential effect will be used to create highly controlled depressions in the surface as part of realizing lattice-matched insulating inclusions for use as gate dielectrics. Diffusion rates of dopant atoms will be enhanced by applying a large field to the sample during flash diffusion. Heating-depth adjustment in flash diffusion will be done by base-temperature choice, or by creating a static temperature gradient in the sample, with the front hotter than the back.

US Patent:

20060151449, Jul 13, 2006

Filed:

Dec 30, 2004

Appl. No.:

11/027579

Inventors:

Raymond Warner - Edina MN, US
Earl Masterson - Guerneville CA, US
Lynn Millar - Guerneville CA, US
John MacCrisken - Palo Alto CA, US
Mark Williams - Austin TX, US

International Classification:

B23K 26/00

US Classification:

219121650

Abstract:

A system and method for parallel-beam scanning a surface. An energetic beam source emits an energetic collimated beam which is received by an optical device, comprising: one or more optical media, operable to receive the emitted beam, such as two pairs of coordinated mirrors or a right prism, and at least one actuator coupled to the one or more optical media, and operable to rotate each of the one or more optical media around a respective axis to perform a parallel displacement of the beam in a respective direction, wherein the respective direction, the beam, and the respective axis are mutually orthogonal. The optical device is operable to direct the beam to illuminate a sequence of specified regions of a surface.

US Patent:

20080192316, Aug 14, 2008

Filed:

Apr 8, 2008

Appl. No.:

12/099642

Inventors:

Raymond M. Warner - Edina MN, US
Earl E. Masterson - Guerneville CA, US
Lynn Millar - Guerneville CA, US
John E. MacCrisken - Palo Alto CA, US
Mark S. Williams - Austin TX, US

International Classification:

G02B 26/08

US Classification:

359196

Abstract:

A system and method for parallel-beam scanning a surface. An energetic beam source emits an energetic collimated beam which is received by an optical device, comprising: one or more optical media, operable to receive the emitted beam, such as two pairs of coordinated mirrors or a right prism, and at least one actuator coupled to the one or more optical media, and operable to rotate each of the one or more optical media around a respective axis to perform a parallel displacement of the beam in a respective direction, wherein the respective direction, the beam, and the respective axis are mutually orthogonal. The optical device is operable to direct the beam to illuminate a sequence of specified regions of a surface.

US Patent:

39940128, Nov 23, 1976

Filed:

Feb 17, 1976

Appl. No.:

5/658307

Inventors:

Raymond M. Warner - Edina MN

Assignee:

The Regents of the University of Minnesota - Minneapolis MN

International Classification:

H01L 2714
H01L 2712

US Classification:

357 30

Abstract:

Apparatus and method for constructing by means of standard high-yield microelectronic batch fabrication processes, reliable, monolithic high-voltage photovoltaic cells and highly efficient photovoltaic arrays therewith. A thin layer of single-crystalline semiconductor material containing a plurality of sublayers defining one or more active junctions in planes parallel to an upper irradiated surface thereof, overlies a supportive insulating substrate body. Widely spaced pairs of elongate heavily doped zones of opposite conductivity types produced by two short diffusion steps extend into the thin layer, defining photovoltaic cells therebetween and providing low-impedance conductive paths for photovoltaic carriers generated in the thin layer to the upper irradiated surface. By overlapping opposite-conductivity pairs of the heavily doped elongate zones, simultaneous dielectric isolation and series connection of adjacent cells is achieved. The elongate zones of individual cells can be interdigitated to decrease parasitic series resistance of the cells.

US Patent:

41908520, Feb 26, 1980

Filed:

Sep 14, 1978

Appl. No.:

5/942152

Inventors:

Raymond M. Warner - Minneapolis MN

International Classification:

H01L 2714

US Classification:

357 30

Abstract:

A photovoltaic semiconductor device which is a horizontal multijunction series-array solar battery with a monocrystalline body and having elongate zones of aluminum doped silicon passed entirely through N-type silicon layers by Thermomigration process to connect together epitaxially grown buried P layers. Masked elongate N diffusion zones which are parallel and substantially contiguous to each elongated P zone penetrates at least through the lowest P layer thereby forming an inactive pn junction. A thin shallow layer of P-type material is diffused across the top N-type layer. Topologically continuous photovoltaic junctions exist in each cell of the photovoltaic semiconductor device between the shallow layer of P-type material, the buried layer or layers of P-type material, the elongate zone of aluminum doped silicon, and the N-type silicon thereby forming active pn junctions. Metallic strips, at the other pn junctions formed by the thermomigrated aluminum which are inactive, electrically connect the cells together. A method is disclosed for manufacturing the photovoltaic semiconductor device.

US Patent:

48686247, Sep 19, 1989

Filed:

Mar 14, 1986

Appl. No.:

6/841012

Inventors:

Bernard L. Grung - Minneapolis MN
Raymond M. Warner - Edina MN
Thomas E. Zipperian - St. Paul MN

Assignee:

Regents of the University of Minnesota - Minneapolis MN

International Classification:

H01L 2972

US Classification:

357 34

Abstract:

A monolithic semiconductor transistor structure is described wherein the active collector region of a bipolar-junction transistor is physically and operatively merged with the channel region of a junction field-effect transistor, providing a composite circuit which approximates a cascode configuration. By controlling the integral of the net impurity doping concentration to various active regions of the device, the active collector region of a bipolar-junction transistor configuration is made sufficiently thin so as to simultaneously function as an active collector region as well as a channel region of one or more field-effect transistors. The channel-collector transistor provides high breakdown voltage, high dynamic resistance and linearity over a wide voltage range, and is compatible with solid-state batch fabrication processes for direct incorporation into larger integrated circuits. The device is particularly suitable for linear applications. Improved operating current is obtained and current limiting constraints of the device are minimized by cooperative emitter and base configurations, topologically extended to maximize use of available circuit area.

US Patent:

47944420, Dec 27, 1988

Filed:

Nov 19, 1985

Appl. No.:

6/799652

Inventors:

Raymond M. Warner - Edina MN
Ronald D. Schrimpf - St. Paul MN
Alfons Tuszynski - San Diego CA

Assignee:

Reagents of the University of Minnesota - Minneapolis MN

International Classification:

H01L 2702
H01L 2980
H01L 2988

US Classification:

357 41

Abstract:

A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+-P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy.

US Patent:

48856150, Dec 5, 1989

Filed:

May 12, 1986

Appl. No.:

6/861708

Inventors:

Raymond M. Warner - Edina MN
Ronald D. Schrimpf - St. Paul MN
Alfons Tuszynski - San Diego CA

Assignee:

Regents of the University of Minnesota - Minneapolis MN

International Classification:

H01L 2980
H01L 2702
H01L 2712

US Classification:

357 22

Abstract:

A single-crystal monolith containing a 3-D doping pattern forming varied devices and circuits that are junction-isolated. The semiconductor monolith includes interconnecting signal paths and power buses, also junction-isolated, usually with N+ regions within P matrix regions, and tunnel junctions, N+ - P+ junctions, as ohmic contacts from N-type to P-type regions. An isolating box incorporates an orthogonal isolator. The 3-D structure places layers of critical profile normal to the growth axis. The orthogonal isolator can include floating elements. The 3-D semiconductor monolith can be manufactured through continuous or quasicontinuous processing in a closed system, such as through MBE or sputter epitaxy. Also, a thin layer of silicide can be provided as an ohmic contact and/or a thick layer of silicide can be provided as a conductor thereby providing monocrystalline 3-D devices or integrated circuits. Finally, an insulator can be provided about an entire device for isolation.