Ravindranadh Tagore Eluri

US Patent:

20230015619, Jan 19, 2023

Filed:

Sep 23, 2022

Appl. No.:

17/952080

Inventors:

- Santa Clara CA, US
Robert MAY - Chandler AZ, US
Sashi KANDANUR - Phoenix AZ, US
Sri Ranga Sai BOYAPATI - Chandler AZ, US
Srinivas PIETAMBARAM - Chandler AZ, US
Steve CHO - Chandler AZ, US
Jung Kyu HAN - Chandler AZ, US
Thomas HEATON - Mesa AZ, US
Ali LEHAF - Phoenix AZ, US
Ravindranadh ELURI - Chandler AZ, US
Hiroki TANAKA - Chandler AZ, US
Aleksandar ALEKSOV - Chandler AZ, US
Dilan SENEVIRATNE - Chandler AZ, US

International Classification:

H01L 23/00
H01L 23/522
H01L 21/768

Abstract:

Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

US Patent:

20210260718, Aug 26, 2021

Filed:

Feb 21, 2020

Appl. No.:

16/797925

Inventors:

- Santa Clara CA, US
Sashi Shekhar Kandanur - Chandler AZ, US
Rahul N. Manepalli - Chandler AZ, US
Ravindranadh T. Eluri - Tempe AZ, US
Dilan Seneviratne - Chandler AZ, US
Clark Linde - Gilbert AZ, US
ABDIAS J. ACOSTA - Maricopa AZ, US
Francoise Bainye Angoua - Chandler AZ, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

B24B 37/04
B24B 37/20

Abstract:

A polishing tool and methodology are disclosed, particularly useful for chemical mechanical polish (CMP) applications (e.g., polishing and planarizing). In an embodiment, the tool includes a carrier structure configured to support a workpiece, a polishing pad configured to rotate and polish at least a portion of the workpiece, a source configured to generate excitation radiation directed towards the workpiece, and a detector configured to receive fluorescence radiation from the workpiece. The fluorescence radiation is generated by absorption of the excitation radiation by a polymer material on the workpiece. The polishing tool also includes a controller configured to, based on a magnitude of the received fluorescence radiation, change at least one operating condition of the polishing tool. For instance, the controller can speed or slow the polishing process, and stop the polishing process when a target thickness is achieved.

US Patent:

20210082797, Mar 18, 2021

Filed:

Sep 29, 2017

Appl. No.:

16/642770

Inventors:

- Santa Clara CA, US
Dilan Seneviratne - Chandler AZ, US
Ravindranadh T. Eluri - Chandler AZ, US

International Classification:

H01L 23/498
H01L 23/00
H01L 21/48

Abstract:

A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than a second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.

US Patent:

20140255293, Sep 11, 2014

Filed:

Mar 11, 2014

Appl. No.:

14/203900

Inventors:

- Corvallis OR, US
Brian K. Paul - Corvallis OR, US
Ravindranadh Tagore Eluri - Corvallis OR, US

International Classification:

C01G 11/02
B06B 3/00

US Classification:

4235661, 422128, 977896, 977773

Abstract:

Apparatuses and methods for synthesizing nanoparticles are provided.

Address:

600 W Grv Pkwy APT 2065, Tempe, AZ 85283

Phone:

541 223-5416

VIN:

4T1BD1FK5CU055564

Make:

TOYOTA

Model:

CAMRY HYBRID

Year:

2012