Ravi Rajagopalan

US Patent:

8443162, May 14, 2013

Filed:

Jan 21, 2005

Appl. No.:

11/040600

Inventors:

Thomas Philip Speier - Holly Springs NC, US
James Norris Dieffenderfer - Apex NC, US
Ravi Rajagopalan - Cary NC, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711170, 711 5, 711128, 711173, 711E12046

Abstract:

Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The configuration tracker configures whether each memory bank is to operate in a cache or not. The bank selector has a plurality of bank distributing functions. Upon receiving an incoming address, the bank selector determines the configuration of memory banks currently operating as the cache and applies an appropriate bank distributing function based on the configuration of memory banks. The applied bank distributing function utilizes bits in the incoming address to access one of the banks configured as being in the cache.

US Patent:

8499208, Jul 30, 2013

Filed:

Oct 27, 2006

Appl. No.:

11/553609

Inventors:

James Norris Dieffenderfer - Apex NC, US
Anand Krishnamurthy - Cary NC, US
Clint Wayne Mumford - Apex NC, US
Jason Lawrence Panavich - Pittsboro NC, US
Ketan Vitthal Patel - Cary NC, US
Ravi Rajagopalan - Cary NC, US
Thomas Philip Speier - Holly Springs NC, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G01R 31/28

US Classification:

714733, 714738

Abstract:

The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

US Patent:

20200065260, Feb 27, 2020

Filed:

Aug 27, 2018

Appl. No.:

16/113141

Inventors:

- San Diego CA, US
Niket CHOUDHARY - Bangalore, IN
Ravi RAJAGOPALAN - Cary NC, US
Patrick EIBL - Durham NC, US
Brian STEMPEL - Raleigh NC, US
David Scott Ray - Austin TX, US
Thomas Philip SPEIER - Wake Forest NC, US

International Classification:

G06F 12/1027

Abstract:

A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.