Ramprasad Satagopan

US Patent:

6373768, Apr 16, 2002

Filed:

Sep 23, 1999

Appl. No.:

09/401988

Inventors:

Steven C. Woo - Saratoga CA
Ramprasad Satagopan - San Jose CA
Richard M. Barth - Palo Alto CA
Ely K. Tsern - Los Altos CA
Craig E. Hampel - San Jose CA

Assignee:

Rambus Inc - Los Altos CA

International Classification:

G11C 704

US Classification:

365211, 365212, 365 63, 365 52

Abstract:

A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

US Patent:

6453401, Sep 17, 2002

Filed:

Jul 2, 1999

Appl. No.:

09/346682

Inventors:

Richard M. Barth - Palo Alto CA
Ramprasad Satagopan - San Jose CA
Anil V. Godbole - Cupertino CA

Assignee:

Rambus Inc. - Mountain View CA

International Classification:

G06F 1200

US Classification:

711167, 711163, 711168, 712500

Abstract:

A memory controller includes a constraint tracking and checking unit for tracking and checking timing constraints imposed by respective issued commands to access a memory. A constraint tracking subunit includes multiple tracking circuits and an allocation circuit. The allocation circuit is configured to allocate a selected tracking circuit from among the multiple tracking circuits each time that a specific command is issued. The allocated tracking circuit is configured to track the timing constraint imposed by the specific command. A constraint checking subunit is configured to determine if the tracked timing constraint is pending against issuance of a generated command to access the memory and to generate a blocking signal when a timing constraint is pending against issuance of a generated command.

US Patent:

6523089, Feb 18, 2003

Filed:

Jul 16, 2001

Appl. No.:

09/907338

Inventors:

Ely K. Tsern - Los Altos CA
Ramprasad Satagopan - San Jose CA
Richard M. Barth - Palo Alto CA
Steven C. Woo - Saratoga CA

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 1200

US Classification:

711118, 711 5, 711105, 713300, 713320, 713323

Abstract:

A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.

US Patent:

6571325, May 27, 2003

Filed:

Sep 23, 1999

Appl. No.:

09/401977

Inventors:

Ramprasad Satagopan - San Jose CA
Richard M. Barth - Palo Alto CA

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 1200

US Classification:

711169, 711 5, 711140, 36523003

Abstract:

A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory system. A physical layer manager in the memory controller insures that physical pins for the memory bus signal channels are available before communicating the timed and sequenced control commands to a target memory device in the memory system.

US Patent:

6640292, Oct 28, 2003

Filed:

Sep 10, 1999

Appl. No.:

09/393884

Inventors:

Richard M. Barth - Palo Alto CA
Ramprasad Satagopan - San Jose CA
Anil V. Godbole - Cupertino CA

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 1200

US Classification:

711168, 711133, 711151, 710 36, 710 52

Abstract:

A system and method for controlling data access in a memory system is disclosed. The memory system is characterized by the use of a transport and retire write request, memory devices incorporating a retire buffer, and inherent data retirement. Addresses associated with un-retired write data are stored in the memory controller and compared to the address of a read request following one or more write requests. Where a read request is directed to an address associated with an un-retired write data, the read request is stalled in the memory controller.

US Patent:

6754783, Jun 22, 2004

Filed:

Feb 18, 2003

Appl. No.:

10/369301

Inventors:

Ely K. Tsern - Los Altos CA
Ramprasad Satagopan - San Jose CA
Richard M. Barth - Ashland OR
Steven C. Woo - Saratoga CA

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 1200

US Classification:

711144, 711 5, 711105, 711118, 713300, 713320, 713323

Abstract:

A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.

US Patent:

6782460, Aug 24, 2004

Filed:

May 27, 2003

Appl. No.:

10/446880

Inventors:

Ramprasad Satagopan - San Jose CA
Richard M. Barth - Palo Alto CA

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 1200

US Classification:

711169, 711 5, 36523003

Abstract:

A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state for receiving and processing the control command. The hazard detector stalls the operation of the control command until the memory bank is in a proper state for receiving and processing the control command. The memory controller also has a command sequencer which sequences control commands to satisfy logical constraints imposed by the memory system, and a timing coordinator to time the communication of the sequenced control commands to satisfy timing requirements imposed by the memory.

US Patent:

7003639, Feb 21, 2006

Filed:

Jun 21, 2004

Appl. No.:

10/873670

Inventors:

Ely K. Tsern - Los Altos CA, US
Ramprasad Satagopan - San Jose CA, US
Richard M. Barth - Ashland OR, US
Steven C. Woo - Saratoga CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F 12/00

US Classification:

711154, 711 5, 711105, 711118, 713300, 713320, 713323

Abstract:

A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.