Rama Gopal Gandham

age ~50

from Poughkeepsie, NY

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Apparatus And Method For Determining Buffered Steiner Trees For Complex Circuits
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US Patent:

6591411, Jul 8, 2003
Filed:

Mar 15, 2001
Appl. No.:

09/810075
Inventors:

Charles Jay Alpert - Austin TX
Rama Gopal Gandham - Wappingers Falls NY
Jiang Hu - Austin TX
Stephen Thomas Quay - Austin TX
Andrew James Sullivan - Wappingers Falls NY
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1750
US Classification:

716 13, 716 2
Abstract:

An apparatus and method for determining buffered Steiner trees for complex circuits is provided. The apparatus and method first clusters sinks with similar characteristics such as criticality, polarity and distance. The purpose of this step is to potentially isolate positive sinks from negative ones and non-critical sinks from critical ones. The present invention then constructs low-level Steiner trees over each of these clusters. Finally, a top-level timing driven Steiner tree is computed where each cluster is treated as a sink. The top-level tree is then merged with the low-level trees to yield a solution for the entire net.

Buffer Insertion With Adaptive Blockage Avoidance
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US Patent:

6898774, May 24, 2005
Filed:

Dec 18, 2002
Appl. No.:

10/324732
Inventors:

Charles Jay Alpert - Round Rock TX, US
Rama Gopal Gandham - Wappingers Falls NY, US
Jiang Hu - College Station TX, US
Stephen Thomas Quay - Austin TX, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F017/50
US Classification:

716 13, 716 2, 716 12, 716 14
Abstract:

A method, computer program product, and data processing system for inserting buffers into integrated circuit routing trees are disclosed. The present invention dynamically modifies a Steiner tree configuration as needed to derive a maximal slack solution that takes into account blockages such as those presented by IP blocks.

Method For Reducing Wiring Congestion In A Vlsi Chip Design
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US Patent:

6958545, Oct 25, 2005
Filed:

Jan 12, 2004
Appl. No.:

10/755590
Inventors:

Pooja M. Kotecha - Wappingers Falls NY, US
Rama Gopal Gandham - Poughkeepsie NY, US
Ruchir Puri - Peekskill NY, US
Louise H. Trevillyan - Katonah NY, US
Adam P. Matheny - Beacon NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L023/52
US Classification:

257758, 257759
Abstract:

A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.

Method And Apparatus For Generating Steiner Trees Using Simultaneous Blockage Avoidance, Delay Optimization And Design Density Management
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US Patent:

7127696, Oct 24, 2006
Filed:

Dec 17, 2003
Appl. No.:

10/738711
Inventors:

Charles Jay Alpert - Round Rock TX, US
Rama Gopal Gandham - Poughkeepsie NY, US
Milos Hrkic - Princeton NJ, US
Stephen Thomas Quay - Austin TX, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

716 10, 716 2, 716 13
Abstract:

A mechanism for constructing Steiner trees using simultaneous blockage avoidance, delay optimization, and design density management are provided. An initial tiled timing-driven Steiner tree is obtained for an integrated circuit design. The Steiner tree is broken into 2-paths for which plates are generated designated the permissible area in which a Steiner point may migrate. Each 2-path is optimized by calculating a cost for each tile in the plate as a function of an environmental cost, a tile delay cost, and a trade-off value. A minimum cost tile is then selected as the point to which the Steiner point in the 2-path, if any, is to migrate. Once each 2-path is processed in this manner, routing is performed so as to minimize the cost at the source. This process may be iteratively repeated with new trade-off values until all of the nets have zero or positive slew.

Method And System For Re-Routing Interconnects Within An Integrated Circuit Design Having Blockages And Bays
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US Patent:

6401234, Jun 4, 2002
Filed:

Dec 17, 1999
Appl. No.:

09/465294
Inventors:

Charles Jay Alpert - Austin TX
Rama Gopal Gandham - Wappingers Falls NY
Jiang Hu - Tianjin, CN
Jose Luis Neves - Wappingers Falls NY
Stephen Thomas Quay - Austin TX
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 1750
US Classification:

716 13
Abstract:

A method and system for re-routing interconnects within an integrated circuit design having blockages and bays is disclosed. A net within the integrated circuit design is initially decomposed into multiple two-paths. The net includes interconnects previously routed by utilizing a Steiner tree routing algorithm. Next, a cost associated with each of the two-paths is calculated. A two-path having a a high cost is subsequently selected and re-routed with a lower cost two-path.