Ram S Viswanath

US Patent:

6493223, Dec 10, 2002

Filed:

Jun 28, 2000

Appl. No.:

09/606840

Inventors:

Ram S. Viswanath - Phoenix AZ
Hong Xie - Phoenix AZ
Robert Sankman - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 720

US Classification:

361690, 361683, 361687, 16510433, 622591

Abstract:

The invention provides a computer with refrigeration. The computer has a housing, a processor, a refrigeration loop and a fan. The processor is located within the housing at a location distant from an air inlet into the housing. The refrigeration loop includes a compressor, a condenser, and expansion valve and an evaporator located in line one after the other. The evaporator is near the air inlet. The fan causes movement of air through the housing. The air passes over the evaporator to cool the air and the processor is primarily cooled by the air.

US Patent:

6575766, Jun 10, 2003

Filed:

Feb 26, 2002

Appl. No.:

10/082881

Inventors:

Hong Xie - Phoenix AZ
Ram Viswanath - Phoenix AZ
PR Patel - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01R 1200

US Classification:

439 70, 439884

Abstract:

A laminated socket contact is described for reducing inductance in power connections to an integrated circuit package. The contact consists of a conductive power panel, a conductive ground panel, a thin non-conductive layer interposed between the power panel and ground panel layer, and at least one conductive finger extending from each of the power panel and ground panel. Various embodiments of this socket contact may be used with power bar connectors, side terminal connectors or pin connectors.

US Patent:

6672880, Jan 6, 2004

Filed:

Dec 19, 2002

Appl. No.:

10/325213

Inventors:

Hong Xie - Phoenix AZ
Ram Viswanath - Phoenix AZ
PR Patel - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01R 1200

US Classification:

439 70

Abstract:

A laminated socket contact is described for reducing inductance in power connections to an integrated circuit package. The contact consists of a conductive power panel, a conductive ground panel, a thin non-conductive layer interposed between the power panel and ground panel layer, and at least one conductive finger extending from each of the power panel and ground panel. Various embodiments of this socket contact may be used with power bar connectors, side terminal connectors or pin connectors.

US Patent:

6854979, Feb 15, 2005

Filed:

Dec 19, 2002

Appl. No.:

10/324534

Inventors:

Hong Xie - Phoenix AZ, US
Ram Viswanath - Phoenix AZ, US
PR Patel - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01R012/00

US Classification:

439 40

Abstract:

A laminated socket contact is described for reducing inductance in power connections to an integrated circuit package. The contact consists of a conductive power panel, a conductive ground panel, a thin non-conductive layer interposed between the power panel and ground panel layer, and at least one conductive finger extending from each of the power panel and ground panel. Various embodiments of this socket contact may be used with power bar connectors, side terminal connectors or pin connectors.

US Patent:

6888722, May 3, 2005

Filed:

Nov 25, 2003

Appl. No.:

10/723108

Inventors:

Ram S. Viswanath - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05H007/20

US Classification:

361704, 165185, 174 163, 257707, 257713, 361708, 361700

Abstract:

An electronic assembly that may include an integrated circuit package that is mounted to a substrate. The assembly may have a thermally conductive phase change material that couples the integrated circuit package to a thermal element. The phase change material may be assembled in a liquid phase to fill any gap between the package and the thermal element. The phase change material may exist in a solid phase during normal operation of the assembly so that the material does not bleed from the package/thermal element interface.

US Patent:

6979208, Dec 27, 2005

Filed:

Aug 19, 2004

Appl. No.:

10/922581

Inventors:

Hong Xie - Phoenix AZ, US
Ram Viswanath - Phoenix AZ, US
Pr Patel - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01R013/648

US Classification:

439101, 439 70

Abstract:

A laminated socket contact is described for reducing inductance in power connections to an integrated circuit package. The contact consists of a conductive power panel, a conductive ground panel, a thin non-conductive layer interposed between the power panel and ground panel layer, and at least one conductive finger extending from each of the power panel and ground panel. Various embodiments of this socket contact may be used with power bar connectors, side terminal connectors or pin connectors.

US Patent:

8513792, Aug 20, 2013

Filed:

Apr 10, 2009

Appl. No.:

12/384984

Inventors:

Sanka Ganesan - Chandler AZ, US
Yosuke Kanaoka - Ibaraki, JP
Ram S. Viswanath - Phoenix AZ, US
Rajasekaran Swaminathan - Tempe AZ, US
Robert M. Nickerson - Chandler AZ, US
Leonel R. Arana - Phoenix AZ, US
John S. Guzek - Chandler AZ, US
Yoshihiro Tomita - Tsukuba, JP

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/02
H01L 23/34
H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257686, 257723, 257773, 257777, 257E25013, 257E23085

Abstract:

Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

US Patent:

20130292838, Nov 7, 2013

Filed:

Jul 10, 2013

Appl. No.:

13/939146

Inventors:

Sanka Ganesan - Chandler AZ, US
Yosuke Kanaoka - Tsukuba-shi, JP
Ram S. Viswanath - Phoenix AZ, US
Rajasekaran Swaminathan - Tempe AZ, US
Robert M. Nickerson - Chandler AZ, US
Leonel R. Arana - Phoenix AZ, US
John S. Guzek - Chandler AZ, US
Yoshihiro Tomita - Tsukuba-shi, JP

International Classification:

H01L 23/488
H01L 21/50

US Classification:

257773, 438109

Abstract:

Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.