Ralph A Schweinfurth

US Patent:

61910163, Feb 20, 2001

Filed:

Jan 5, 1999

Appl. No.:

9/226503

Inventors:

Robert S. Chau - Beaverton OR
Thomas Letson - Beaverton OR
Patricia Stokley - Aloha OR
Peter Charvat - Portland OR
Ralph Schweinfurth - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 213205
H01L 214763

US Classification:

438585

Abstract:

A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.