Rakesh R Vallishayee from 3300 Vittoria Loop, Pleasanton, CA 94568, age 54, Phone: 408 227-1387

Us Patents

Designing An Integrated Circuit To Improve Yield Using A Variant Design Element
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US Patent:

7487474, Feb 3, 2009
Filed:

Nov 17, 2003
Appl. No.:

10/541076
Inventors:

Dennis Ciplickas - San Jose CA, US
Joe Davis - Unterschleissheim, DE
Christopher Hess - San Ramon CA, US
Sherry Lee - San Jose CA, US
Enrico Malavasi - Mountain View CA, US
Ratibor Radojcic - San Diego CA, US
Brian Stine - Los Altos Hills CA, US
Rakesh Vallishayee - San Jose CA, US
Stefano Zanella - San Jose CA, US
Nicola Dragone - Vobarno, IT
Carlo Guardiani - Verona, IT
Michel Quarantelli - Noceto, IT
Stefano Tonello - Breganze, IT
Joshi Aniruddha - Irvine CA, US
Assignee:

PDF Solutions, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 2, 716 4, 716 5, 716 19, 716 20, 716 21
Abstract:

An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.

Method For Reducing Layout Printability Effects On Semiconductor Device Performance
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US Patent:

7644388, Jan 5, 2010
Filed:

Sep 29, 2006
Appl. No.:

11/540453
Inventors:

Lidia Daldoss - San Jose CA, US
Sharad Saxena - Richardson TX, US
Christoph Dolainsky - Wessling, DE
Rakesh R. Vallishayee - San Jose CA, US
Assignee:

PDF Solutions, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 21, 716 4, 716 5, 716 19
Abstract:

A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or parametric failure in a semiconductor device is identified in the mask layout. A test structure representative of the identified layout configuration is obtained. A design of experiment is associated with the test structure. The design of experiment is defined to investigating effects of variations of one or more layout attributes in the test structure. Multiple instance of the test structure are fabricated on a wafer according to the design of experiment. Electrical performance characteristics of the fabricated test structures are measured. Based on the measured electrical performance characteristics, one or more layout attributes of the test structure capable of causing functional or parametric failure are determined.

Method For Improving Mask Layout And Fabrication
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US Patent:

7434197, Oct 7, 2008
Filed:

Oct 28, 2005
Appl. No.:

11/262148
Inventors:

Christoph Dolainsky - Wessling, DE
Jonathan O. Burrows - San Jose CA, US
Dennis Ciplickas - San Jose CA, US
Joseph C. Davis - San Jose CA, US
Rakesh Vallishayee - San Jose CA, US
Howard Read - San Jose CA, US
Christopher Hess - San Carlos CA, US
Assignee:

PDF Solutions, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 19, 716 21
Abstract:

A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identified hot spot. The test structure is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies. The test structure is fabricated on a test wafer using specified fabrication processes. The as-fabricated test structure is examined to identify one or more adjustments to either the feature geometries of the hot spot of the mask layout design or the specified fabrication processes, wherein the identified adjustments are capable of reducing the fabrication deficiencies.

Integrated Circuit Containing Does Of Ncem-Enabled Fill Cells
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US Patent:

20170178981, Jun 22, 2017
Filed:

Apr 4, 2016
Appl. No.:

15/090256
Inventors:

- San Jose CA, US
Dennis Ciplickas - San Jose CA, US
Tomasz Brozek - Morgan Hill CA, US
Jeremy Cheng - San Jose CA, US
Simone Comensoli - Darfo Boario Terme, IT
Indranil De - Mountain View CA, US
Kelvin Doong - Hsinchu City, TW
Hans Eisenmann - Tutzing, DE
Timothy Fiscus - New Galilee PA, US
Jonathan Haigh - Pittsburgh PA, US
Christopher Hess - Belmont CA, US
John Kibarian - Los Altos Hills CA, US
Sherry Lee - Monte Sereno CA, US
Marci Liao - Santa Clara CA, US
Sheng-Che Lin - Hsinchu City, TW
Hideki Matsuhashi - Santa Clara CA, US
Kimon Michaels - Monte Sereno CA, US
Conor O'Sullivan - Campbell CA, US
Markus Rauscher - Munich, DE
Vyacheslav Rovner - Pittsburgh PA, US
Andrzej Strojwas - Pittsburgh PA, US
Marcin Strojwas - Pittsburgh PA, US
Carl Taylor - Pittsburgh PA, US
Rakesh Vallishayee - Dublin CA, US
Larg Weiland - Hollister CA, US
Nobuharu Yokoyama - Tokyo, JP
International Classification:

H01L 21/66
Abstract:

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).