Rahul E Mishra

US Patent:

8299533, Oct 30, 2012

Filed:

Nov 24, 2010

Appl. No.:

12/954155

Inventors:

Shunhua Chang - South Burlington VT, US
Kiran V. Chatty - Starkville MS, US
Junjun Li - Williston VT, US
Rahul Mishra - Essex Junction VT, US
Mujahid Muhammad - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/62

US Classification:

257355, 438133, 257E29181

Abstract:

A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

US Patent:

8350329, Jan 8, 2013

Filed:

Oct 19, 2010

Appl. No.:

12/907105

Inventors:

Shunhua T. Chang - South Burlington VT, US
Kiran V. Chatty - Williston VT, US
Junjun Li - Williston VT, US
Rahul Mishra - Essex Junction VT, US
Mujahid Muhammad - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/60
H01L 21/8238

US Classification:

257355, 257E27062, 257E21632, 438199

Abstract:

An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the second polarity type is formed above the buried layer. An FET of the first polarity type is formed within the well region. An inner pair of shallow wells of the first polarity type is disposed adjacent to source and drain diffusion regions of the FET, the inner pair of shallow wells having a depth such that a bottom of the inner pair of shallow wells is above a top of the buried layer. An outer pair of deep wells of the first polarity type extends down to the top of the buried layer such that the outer pair of deep wells and the buried layer define a perimeter of the well region of the second polarity type.

US Patent:

8354722, Jan 15, 2013

Filed:

May 31, 2011

Appl. No.:

13/149174

Inventors:

Shunhua Chang - South Burlington VT, US
Kiran V. Chatty - Oviedo FL, US
Junjun Li - Williston VT, US
Rahul Mishra - Essex Junction VT, US
Mujahid Muhammad - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/78
H01L 29/788
H02H 9/00

US Classification:

257355, 257356, 257357, 257362, 257371, 257565, 257E27018, 257E27063, 257E27067, 257E2711, 257E29225, 361 56, 361111, 361118, 438133, 438135, 438200

Abstract:

An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

US Patent:

8377754, Feb 19, 2013

Filed:

Oct 10, 2011

Appl. No.:

13/269819

Inventors:

Junjun Li - Williston VT, US
Rahul Mishra - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/332

US Classification:

438133, 257E29181, 257107, 438140

Abstract:

A method of forming an IC device including a latchup silicon controlled rectifier (SCR) includes forming a mask on a top surface of a substrate, wherein the mask covers a first portion of the substrate and exposes a second portion of the substrate that is located in one of an n-well and a p-well on the substrate; etching the exposed second portion of the substrate to form an etched area; forming a stress engineered junction of the latchup SCR by selective epitaxial deposition in the etched area; and removing the mask.

US Patent:

8513738, Aug 20, 2013

Filed:

Jul 21, 2011

Appl. No.:

13/188094

Inventors:

Shunhua T. Chang - South Burlington VT, US
Kiran V. Chatty - Oviedo FL, US
Junjun Li - Williston VT, US
Rahul Mishra - Essex Junction VT, US
Mujahid Muhammad - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/60

US Classification:

257358, 438286, 438305, 438179, 257E29012, 257E29279, 257E21619, 257363, 257408

Abstract:

An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.

US Patent:

8614489, Dec 24, 2013

Filed:

Sep 13, 2012

Appl. No.:

13/614072

Inventors:

John B. Campi - Westford VT, US
Shunhua Thomas Chang - South Burlington VT, US
Kiran V. Chatty - Williston VT, US
Junjun Li - Williston VT, US
Rahul Mishra - Essex Junction VT, US
Mujahid Muhammad - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257378, 257E27031

Abstract:

A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

US Patent:

20120250195, Oct 4, 2012

Filed:

Mar 31, 2011

Appl. No.:

13/076625

Inventors:

Shunhua T. Chang - South Burlington VT, US
Kiran V. Chatty - Williston VT, US
Junjun Li - Williston VT, US
Rahul Mishra - Essex Junction VT, US
Mujahid Muhammad - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H02H 9/04

US Classification:

361 56

Abstract:

An ESD power clamp circuit and method of ESD protection. The ESD power clamp circuit includes: a power clamp device coupled to a resistive/capacitive (RC) network, the RC network including a capacitor as the capacitive element of the RC network and one or more junction field effect transistors (JFETs) configured as variable resistors as the resistive element of the RC network.

US Patent:

20130126911, May 23, 2013

Filed:

Jan 17, 2013

Appl. No.:

13/743392

Inventors:

International Business Machines Corporation - Armonk NY, US
Junjun Li - Williston VT, US
Rahul Mishra - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/66

US Classification:

257 77

Abstract:

A latchup silicon controlled rectifier (SCR) includes a p+ region and an n+ region located in a p-well of the latchup SCR; and a p+ region and an n+ region located in a n-well of the latchup SCR, wherein the latchup SCR further comprises one of embedded silicon germanium (eSiGe) in the p+ region in the n-well of the latchup SCR and silicon carbide (SiC) in the n+ region in the p-well of the latchup SCR.