The University of Texas at Austin
Associate Professor at the University of Texas at Austin
The University of Texas at Austin
Assistant Professor
Education:
University of Minnesota 2001 - 2007
Doctorates, Doctor of Philosophy, Business
Indian Institute of Foreign Trade 1996 - 1998
Master of Business Administration, Masters, International Business
Sardar Vallabhbhai National Institute of Technology, Surat 1991 - 1995
Bachelor of Engineering, Bachelors, Electrical Engineering
Kendriya Vidyalaya 1987 - 1991
Uhnder, Inc.
Senior Director, Software
Amd Mar 2014 - Sep 2015
Senior Director, Embedded Engineering Solutions
Amd Oct 2010 - Mar 2014
Senior Director, Developer Solutions
Spi Software Technologies Feb 2006 - Sep 2010
Managing Director
Stream Processors, Inc. Nov 2004 - Jul 2009
Vice President and Gm, Solutions
Education:
Illinois Institute of Technology 1991 - 1993
Illinois Institute of Technology 1990 - 1991
Pg Center, Kolar 1986 - 1990
Bachelor of Engineering, Bachelors, Engineering
Madras Medical College
Bachelors, Bachelor of Medicine
Pu Liu - Austin TX Raghunath Rao - Austin TX Miroslav Dokic - Austin TX
Assignee:
Cirrus Logic, Inc.
International Classification:
G10L 2100
US Classification:
704500, 704504
Abstract:
A method of managing multiple channels of audio data in an audio system having multiple speakers. A first channel signal is selectively passed through a software high-pass filter to selectively drive a first one of the speakers. A plurality of channel signals are selectively summed in software to generate a composite signal and the composite signal passed through a software low-pass filter to selectively drive a second one of the speakers.
Methods And Circuits For Synchronizing Streaming Data And Systems Using The Same
A method for synchronizing stream processing with a locally generated system time clock is disclosed. A program clock reference is recovered from a transport layer and used to vary the frequency of the locally generated system time clock. A presentation time stamp is recovered from a packetized elementary stream derived from the transport layer. The relationship between a reference sample associated with the presentation time stamp from the packetized elementary stream and a current sample being streamed is determined relative to the system time clock. Data samples are added or subtracted from a stream of data samples being streamed in response to the step of determining to establish a relationship between the stream of samples and the presentation time stamp relative to the system time clock.
Accessing Shared Memory Using Token Bit Held By Default By A Single Processor
Raghunath Rao - Austin TX Miroslav Dokic - Austin TX Zheng Luo - Austin TX Jeffrey Niehaus - Austin TX James Divine - Austin TX
Assignee:
Cirrus Logic, Inc.
International Classification:
G06F 1200
US Classification:
711151, 711152
Abstract:
A method of operating shared memory in a multiple processor system. A token is by default maintained with a first processor, the token enabling access to shared memory. A determination is made that a second processor requires access to shared memory. A determination is also made as to whether the first processor is accessing to the shared memory. The token is transferred the second processor if the first processor is not accessing the shared memory. The second processor accesses the shared memory with the token.
Vladimir Mesarovic - Austin TX Raghunath Krishna Rao - Austin TX Miroslav Dokic - Austin TX Sachin Sunil Deo - Austin TX Nariankadu Datareya Hemkumar - Rochester MN
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 700
US Classification:
341106, 341 51
Abstract:
A method of decoding an encoded bitstream. The method includes performing a two-table lookup. A first table is addressed in response to a first plurality of bits from the bitstream. An address into a second table is generated using a value in an entry in said first table accessed in the addressing step. A value (representing the decoded value corresponding to the codeword in the bitstream) in an entry in said second table at the address from the generating step is output.
Methods For Surround Sound Simulation And Circuits And Systems Using The Same
A method of producing reverberation effects is disclosed. A filter is implemented for modeling early acoustic reflections in response to an input signal using a first processor, the filter includes a delay buffer of a selected length and having a selected number of taps for tapping samples of corresponding amounts of delay and a summer for summing the tapped samples to generate a filter output signal. A reverberator is implemented for modeling late acoustic reflections using a second processor, the reverberator receiving the filter output and generating a plurality of output signals.
Systems And Methods For Transmitting Bursty-Asnychronous Data Over A Synchronous Link
Miroslav Dokic - Austin TX Sanjay Joshi - Austin TX Vladimir Mesarovic - Austin TX Raghunath Rao - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G01L 1900
US Classification:
704500, 370350
Abstract:
A method for transferring data bursts via a synchronous data link includes the step of receiving a burst of packets, each packet including a header and a frame of data compressed at a selected sampling rate and transmitted at a selected bit rate. At least one of the packets of the stream of packets is embedded into a carrier frame including a carrier frame header. The carrier frame is then transmitted via the synchronous link. The data frame is extracted from the carrier frame and decompressed at the sample rate.
Raghunath Rao - Austin TX, US Narsimham Gangishetti - Austin TX, US Miroslav Dokic - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G06F017/00 H03G005/00
US Classification:
700 94, 381 98
Abstract:
Digital tone controls include a first path including a digital filter and a scaler for controlling a level of a low frequency component of a received digital audio signal. A second includes a digital filter and a scaler for controlling a level of a high frequency component of the received digital audio signal. A third path includes a scaler for controlling a level of an unfiltered component of the received audio signal. A summer adds a contribution from each of the paths to generate a composite signal having a selected gain-frequency response.
Circuits And Methods For Debugging An Embedded Processor And Systems Using The Same
Sanjay Ramakrishna Pillay - Austin TX, US Raghunath Krishna Rao - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G06F011/00
US Classification:
714 34, 714 30, 714 47
Abstract:
A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.