Rafael B Castro

US Patent:

7340541, Mar 4, 2008

Filed:

Sep 8, 2004

Appl. No.:

10/936088

Inventors:

Rafael Castro - Round Rock TX, US
Andrew B. Moch - Pfugerville TX, US
Sean M. Nickel - Pittsburgh PA, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 13/00

US Classification:

710 31, 710 52, 710 58, 326 93, 326 94

Abstract:

A system and method for buffering bidirectional digital input/output (I/O) lines. The system (e. g. , data acquisition system) may comprise a device including circuitry for buffering bidirectional digital lines. A first integrated circuit (IC) of the device includes a first and a second bidirectional buffer coupled to a first bidirectional digital I/O line, and a second IC of the device includes a third bidirectional buffer. The first IC and the second IC each include a control unit to control the driving direction of the corresponding bidirectional buffers independently to change the direction of the data flow through the first bidirectional digital I/O line from the output direction to the input direction or vice versa. The driving direction of the bidirectional buffers are changed at different times in a particular sequence, and the order depends on whether the direction change is from the output direction to the input direction or vice versa.

US Patent:

7644207, Jan 5, 2010

Filed:

Jun 29, 2007

Appl. No.:

11/770807

Inventors:

Rafael Castro - Round Rock TX, US
Haider A. Khan - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 3/00
G06F 5/00
G06F 13/12
G06F 13/38

US Classification:

710 60, 710 40, 710 62, 710 69

Abstract:

An isolated data acquisition device including a plurality of data acquisition channels, an isolated system management unit coupled to the data acquisition channels, a host system management unit, a serial bus coupled to the host system management unit and the isolated system management unit, and isolation circuitry coupled to the serial bus. The isolation circuitry electrically isolates the host system management unit from the isolated system management unit and the data acquisition channels. During operation, the isolated system management unit and the host system management unit may each store data associated with one or more pending bus transactions. Each of the system management units may select at least one of the pending bus transactions according to a predetermined priority scheme, encode and serialize the data associated with the selected bus transaction, and transmit the serialized data across the isolation circuitry to the other system management unit via the serial bus.

US Patent:

7649726, Jan 19, 2010

Filed:

Sep 8, 2004

Appl. No.:

10/936632

Inventors:

Rafael Castro - Round Rock TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

H02H 7/00

US Classification:

361119, 361111

Abstract:

A protection circuit for protecting a device from destructive electrical conditions, such as ESD, over-voltage, and over-current, while keeping the output impedance of the device's I/O lines to a minimum, and self-regulating power dissipation. The device may comprise a first protection circuit and a second protection circuit coupled to each of one or more I/O lines for providing a primary and a secondary level of protection, respectively, for the I/O lines. The first protection circuit of the device may combine the use of Schottky diodes for voltage clamping, with a current limiting device for self-regulating the power dissipation. The current limiting device may be operable to function as a small, low impedance resistor in a normal operating range and as a controlled power dissipater outside the normal operating range. The device may be a data acquisition device comprised in a data acquisition system.

US Patent:

8176351, May 8, 2012

Filed:

Jun 26, 2007

Appl. No.:

11/768255

Inventors:

Rafael Castro - Round Rock TX, US
Brian Keith Odom - Georgetown TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

H04B 1/38

US Classification:

713400, 713401, 713500, 713501, 713502, 713503, 713600, 713601, 375222, 375223, 375225, 327156

Abstract:

One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During operation, at least one of the counter units may receive a measurement signal (or input signal) acquired by the data acquisition device and also a sample clock signal. The counter unit may sample the measurement signal based on the selected operational mode and timing of the sample clock, and at a rate that is independent of the frequency of the measurement signal. Furthermore, the counter unit may sample the measurement signal based on a selected one of a plurality of timing modes associated with the sample clock signal. The counter units may take samples of the measurement signal to perform at least one of the following types of measurements: period, frequency, pulse-width, semi-period, time separation, or event counting.

US Patent:

20060197607, Sep 7, 2006

Filed:

Feb 22, 2005

Appl. No.:

11/063141

Inventors:

Rafael Castro - Austin TX, US

International Classification:

H03L 7/00

US Classification:

331016000

Abstract:

A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subsystems. The subsystems may be comprised in the data acquisition device or may be external to the data acquisition device. The real-time monitoring circuit may receive a plurality of timing signals from the plurality of subsystems and may select a control loop timing signal out of the plurality of timing signals. The real-time monitoring circuit may determine whether the operations of the control loop are performed within a particular period of time by monitoring the control loop timing signal and communicating with the processing unit. In response to an error notification, the processing unit may take appropriate action, such as shutting down the system and/or reporting an error or warning.

Author:

Rafael Martinez Castro

ISBN #:

8481214434