Piotr Szabelski

US Patent:

6374323, Apr 16, 2002

Filed:

Nov 12, 1999

Appl. No.:

09/439303

Inventors:

Henry Stracovsky - San Jose CA
Piotr Szabelski - Santa Clara CA

Assignee:

Infineon Technologies AG - Munich

International Classification:

G06F 1200

US Classification:

711 5, 711105, 711167, 711168, 36523003, 365233

Abstract:

Computer memory conflict avoidance using a plurality of page registers coupled individually to a plurality of memory banks is described. An incoming system address request containing a requested memory bank number and a requested page number is received by the memory controller. The page register number corresponding to the requested memory bank is located and the open page address in the located page register is compared to the requested page address. If the requested page number corresponds to the open page address, it is then accessed. If it does not match, the memory page corresponding to the requested page address is closed, the memory page corresponding to the requested page address is opened and then accessed.

US Patent:

6378049, Apr 23, 2002

Filed:

Nov 12, 1999

Appl. No.:

09/439254

Inventors:

Henry Stracovsky - San Jose CA
Piotr Szabelski - Santa Clara CA

Assignee:

Infineon Technologies A.G. - Munich

International Classification:

G06F 1200

US Classification:

711147, 710 8

Abstract:

According to the present invention, a method for controlling access to a memory device is disclosed. A requesting system is identified, the configurable system interface is then configured in order to accommodate the identified requesting system and a memory access request is generated by the requesting system. A universal command is generated by the configurable system interface based upon the memory access request which is then converted from the universal command to a sequenced universal command by the command sequencer based upon both the current state of the memory device as indicated by the corresponding resource tag and the operating characteristic of the memory as indicated by the corresponding the characteristic operating parameter. The memory is then accessed using the sequenced universal command.

US Patent:

6385708, May 7, 2002

Filed:

Nov 12, 1999

Appl. No.:

09/439857

Inventors:

Henry Stracovsky - San Jose CA
Piotr Szabelski - Santa Clara CA

Assignee:

Infineon Technologies AG - Munich

International Classification:

G06F 1200

US Classification:

711167, 711154, 711151, 711158, 709103

Abstract:

According to the present invention, a scheduler that uses a timing-look-up-table and page timers to determine the time between two consecutive memory accesses is described. The scheduler for scheduling a plurality of commands to an associated memory, the memory comprising a plurality of M memory banks and a plurality of N memory pages includes restriction circuitry for determining an earliest issue time for each command based at least in part on access delays associated with others of the commands corresponding to a same memory bank and reordering circuitry for determining an order in which the commands should be transmitted to the associated memory with reference to the earliest issue time associated with each command and a data occurrence time associated with selected ones of the commands.

US Patent:

6430642, Aug 6, 2002

Filed:

Nov 27, 2000

Appl. No.:

09/723750

Inventors:

Henry Stracovsky - San Jose CA
Piotr Szabelski - Santa Clara CA

Assignee:

Infineon Technologies AG - Munich

International Classification:

G06F 1200

US Classification:

710244, 710 40, 710 41, 710107, 710110, 710112, 710113, 709222, 709232

Abstract:

According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of requesting device requests of the external devices, a request queue controller unit coupled to the request queue suitably arranged to fetch any of the requests stored therein, a responds queue suitably arranged to store any number of responses from the external devices. The apparatus also includes a responds queue controller unit coupled to the responds queue suitably arranged to fetch any of the requests stored therein; wherein each of the responds and its associated request have associated with them a group identification number indicating a particular group of requesting devices from which the request originated and the corresponding response is destined, wherein the responds queue controller and the request queue controller units use a priority number stored in a group priority selector register to prioritize each of the stored requests and responses, such that a request or response having a higher priority bypasses a request or response having a lower priority.

US Patent:

6453370, Sep 17, 2002

Filed:

Nov 12, 1999

Appl. No.:

09/439591

Inventors:

Henry Stracovsky - San Jose CA
Piotr Szabelski - Santa Clara CA

Assignee:

Infineion Technologies AG - Munich

International Classification:

G06F 1200

US Classification:

710 36, 710 17, 710 19, 710 23, 710 28, 710 29, 710 37, 710200, 711100, 711147, 711150, 711152, 711153, 711154, 711156, 711163, 711168, 711210

Abstract:

A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.

US Patent:

6510474, Jan 21, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/439866

Inventors:

Henry Stracovsky - San Jose CA
Piotr Szabelski - Santa Clara CA

Assignee:

Infineon Technologies AG - Munich

International Classification:

G06F 1300

US Classification:

710 58, 710 5, 710 6, 710 40, 710 41, 710116, 710123, 710244, 709100, 709102, 709103, 711158, 711167

Abstract:

According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests are described. In one embodiment, a method of increasing data bandwidth by reordering incoming memory requests in order to avoid gaps between commands on a command bus and data packets on a data bus while maintaining the original incoming memory request order is disclosed. A best position in a command queue is calculated for each new incoming command by a reordering block coupled to the command queue. Read data is stored in a data queue while the associated incoming commands are stored in their respective original order in a FIFO register included in a re-reordering block. The data is stored in its original order in a data queue while incoming data from the memory is stored in a read-data buffer included in the re-reordering block according to the order stored in the data queue. The stored commands are sent to the processor according to the order stored in the FIFO such that the data to the processor will be issued in the same order as incoming from processor commands.

US Patent:

6526484, Feb 25, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/439253

Inventors:

Piotr Szabelski - Santa Clara CA

Assignee:

Infineon Technologies AG - Munich

International Classification:

G06F 1200

US Classification:

711158, 710 39, 710 40

Abstract:

According to the present invention, a scheduler suitable for reordering of memory requests to achieve higher average utilization of the command and data bus is described. The scheduler for scheduling a plurality of commands to an associated memory, the memory comprising a plurality of M memory banks and a plurality of N memory pages includes restriction circuitry for determining an earliest issue time for each command based at least in part on access delays associated with others of the commands corresponding to a same memory bank and reordering circuitry for determining an order in which the commands should be transmitted to the associated memory with reference to the earliest issue time associated with each command and a data occurrence time associated with selected ones of the commands.

US Patent:

6532505, Mar 11, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/439544

Inventors:

Henry Stracovsky - San Jose CA
Piotr Szabelski - Santa Clara CA

Assignee:

Infineon Technologies AG - Munich

International Classification:

G06F 1312

US Classification:

710 63, 710 5, 710 6, 710 15, 710 17, 710 18, 710 19, 710 40, 710 62, 710240, 710244, 711100, 711147, 711150

Abstract:

A universal access controller is described. The universal resource access controller is coupled to a requesting system and a resource, such that when the requesting system desires access to the resource, the requesting system generates a resource access request which is passed to the universal resource controller. The universal resource controller, in turn, uses a specific characteristic operating parameter of the requested resource as well as a current state of the requested resource to generate a corresponding sequenced universal access request command suitable for accessing the resource as required by the requesting system.