Phuc M Nguyen

US Patent:

20200272823, Aug 27, 2020

Filed:

Nov 5, 2018

Appl. No.:

16/625172

Inventors:

- Mountain View CA, US
Gautam Prasad - Los Angeles CA, US
Phuc Xuan Nguyen - San Francisco CA, US
Bohyung Han - Songpa-Gu, Seoul, KR

International Classification:

G06K 9/00
G06K 9/62

Abstract:

Systems and methods for a weakly supervised action localization model are provided. Example models according to example aspects of the present disclosure can localize and/or classify actions in untrimmed videos using machine-learned models, such as convolutional neural networks. The example models can predict temporal intervals of human actions given video-level class labels with no requirement of temporal localization information of actions. The example models can recognize actions and identify a sparse set of keyframes associated with actions through adaptive temporal pooling of video frames, wherein the loss function of the model is composed of a classification error and a sparsity of frame selection. Following action recognition with sparse keyframe attention, temporal proposals for action can be extracted using temporal class activation mappings, and final time intervals can be estimated corresponding to target actions.

US Patent:

20170084682, Mar 23, 2017

Filed:

Dec 7, 2016

Appl. No.:

15/371488

Inventors:

- AUSTIN TX, US
PHUC M. NGUYEN - AUSTIN TX, US
DOUGLAS M. REBER - AUSTIN TX, US

International Classification:

H01L 49/02
H01L 23/482
H01L 23/00
H01L 23/485
H01L 23/31

Abstract:

A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

US Patent:

20160089574, Mar 31, 2016

Filed:

Sep 28, 2015

Appl. No.:

14/868268

Inventors:

- New York NY, US
Jeffrey Scott BRUENING - Los Angeles CA, US
Gordon THOMPSON, III - New York NY, US
Chirag PATEL - Brooklyn NY, US
Neel Magan BAKARANIA - Forest Hills NY, US
Phuc Van Nguyen - Brooklyn NY, US
Catherine Crowe MARK - New York NY, US
John WHITE - Brooklyn, NY
Jin Sung YOO - Brooklyn NY, US
Karen RAINERT - Mamaroneck NY, US
John Paul BENVENUTO - New York NY, US
Nicole DEL SENNO - Flushing NY, US
Matthew JACOBS - New York NY, US
David HITCHINGS - Kinnelon NJ, US

International Classification:

A63B 24/00

Abstract:

Exercise class systems and methods may include a plurality of pieces of exercise equipment and/or a plurality of sensing systems adapted to be worn on people in the class, each piece of equipment or sensing system outputting plural exercise signals relating to exercise performance on the piece of equipment or of the person with the sensing system. A computer system may also be provided. The computer system may include at least one electronic storage device which stores the plural signals from the pieces of equipment or sensing system and at least one processor which generates an output signal containing an animation corresponding to at least two of the exercise signals from each of the pieces of equipment or sensing systems. At least one display device, visible from each of the pieces of equipment or people in the class, may receive the output signal and display the animation.

US Patent:

20160064294, Mar 3, 2016

Filed:

Aug 27, 2014

Appl. No.:

14/470383

Inventors:

DOUGLAS M. REBER - Austin TX, US
Sergio A. Ajuria - Austin TX, US
Phuc M. Nguyen - Austin TX, US

International Classification:

H01L 21/66
H01L 21/48
H01L 23/00

Abstract:

An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.

US Patent:

20150200146, Jul 16, 2015

Filed:

Jan 13, 2014

Appl. No.:

14/153417

Inventors:

Douglas M. Reber - Austin TX, US
Sergio A. Ajuria - Austin TX, US
Phuc M. Nguyen - Austin TX, US

International Classification:

H01L 21/66
H01L 23/00
H01L 23/29
H01L 23/10
H01L 21/78

Abstract:

Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

US Patent:

20150061709, Mar 5, 2015

Filed:

Aug 27, 2013

Appl. No.:

14/011160

Inventors:

Sergio A. Ajuria - Austin TX, US
Phuc M. Nguyen - Austin TX, US
Douglas M. Reber - Austin TX, US

International Classification:

G01R 31/28

US Classification:

3247503

Abstract:

A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.

Address:

9500 Bolsa Ave STE M, Westminster, CA 92683

Phone:

714 531-8915

VIN:

5UXFE43539L267900

Make:

BMW

Model:

X5

Year:

2009