Philippe D Vandermersch

US Patent:

7428223, Sep 23, 2008

Filed:

Sep 26, 2001

Appl. No.:

09/965375

Inventors:

Florian Patrick Nierhaus - Sunnyvale CA, US
Philippe Vandermersch - San Jose CA, US

Assignee:

Siemens Corporation - Iselin NJ

International Classification:

H04L 12/16
H04Q 11/00
H04M 3/42

US Classification:

370260, 370263, 370267, 37920201

Abstract:

The present invention is directed to a system and method for background noise reduction and performance improvement in conferencing. A method for providing a conferencing session may include receiving inputs from a number of participants in a conferencing session. A number of prominent inputs are determined from the received inputs and the determined prominent inputs are combined into a first output stream. The output stream is suitable for being sent to at least one participant of the number of participants in the conferencing session.

US Patent:

20030063573, Apr 3, 2003

Filed:

Jan 24, 2002

Appl. No.:

10/056776

Inventors:

Philippe Vandermersch - San Jose CA, US

International Classification:

H04L012/16

US Classification:

370/260000, 455/416000, 370/261000

Abstract:

The present invention is directed to a system and method for handling larger number of people per conference in voice conferencing over packetized networks. A method for providing a conferencing session may include receiving inputs from a number of participants in a conferencing session. The received inputs are combined into an output packet including at least two sub-packets. The sub-packets having payloads including mixed received inputs from the number of participants. The payloads of at least two of the sub-packets contain different mixed received inputs.

US Patent:

20220300578, Sep 22, 2022

Filed:

Jun 7, 2022

Appl. No.:

17/834427

Inventors:

- Santa Clara CA, US
Philippe Vandermersch - San Jose CA, US

International Classification:

G06F 17/16
G06F 9/30
G06N 5/04
G06N 3/08

Abstract:

Apparatuses, systems, and techniques to determine a matrix multiplication algorithm for a matrix multiplication operation. In at least one embodiment, a matrix multiplication operation is analyzed to determine an appropriate matrix multiplication algorithm to perform the matrix multiplication algorithm.

US Patent:

20210406342, Dec 30, 2021

Filed:

Sep 9, 2021

Appl. No.:

17/471126

Inventors:

- Santa Clara CA, US
Philippe Vandermersch - San Jose CA, US

International Classification:

G06F 17/16
G06F 9/30
G06N 5/04
G06N 3/08

Abstract:

Apparatuses, systems, and techniques to determine a matrix multiplication algorithm for a matrix multiplication operation. In at least one embodiment, a matrix multiplication operation is analyzed to determine an appropriate matrix multiplication algorithm to perform the matrix multiplication algorithm.

US Patent:

20210256092, Aug 19, 2021

Filed:

Feb 19, 2020

Appl. No.:

16/795380

Inventors:

- Santa Clara CA, US
Philippe Vandermersch - San Jose CA, US

International Classification:

G06F 17/16
G06F 9/30
G06N 3/08
G06N 5/04

Abstract:

Apparatuses, systems, and techniques to determine a matrix multiplication algorithm for a matrix multiplication operation. In at least one embodiment, a matrix multiplication operation is analyzed to determine an appropriate matrix multiplication algorithm to perform the matrix multiplication algorithm.

US Patent:

20140196043, Jul 10, 2014

Filed:

Jan 9, 2013

Appl. No.:

13/737287

Inventors:

- Santa Clara CA, US
Sharanyan Chetlur - Banglore, IN
Lung Sheng Chien - Santa Clara CA, US
Robert Strzodka - Santa Clara CA, US
Philippe Vandermersch - Santa Clara CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 9/46

US Classification:

718100

Abstract:

A system and method for re-factorizing a square input matrix on a parallel processor. In one embodiment, the system includes: (1) a matrix generator operable to generate an intermediate matrix by embedding a permuted form of the input matrix in a zeroed-out sparsity pattern of a combination of lower and upper triangular matrices resulting from a prior LU factorization of a previous matrix having a same sparsity pattern, reordering to minimize fill-in and pivoting strategy as the input matrix and (2) a re-factorizer associated with the matrix generator and operable to use parallel threads to apply an incomplete-LU factorization with zero fill-in on the intermediate matrix.