Philip Rosen

Author:

Philip T. Rosen

ISBN #:

0313212317

Author:

Philip T. Rosen

ISBN #:

0313243484

Author:

Philip T. Rosen

ISBN #:

0313270031

Author:

Philip Rosen

ISBN #:

0231058810

Author:

Philip Rosen

ISBN #:

0231058802

Author:

Philip Rosen

ISBN #:

0268014515

Author:

Philip Rosen

ISBN #:

0268014523

Author:

Philip Rosen

ISBN #:

0313270376

US Patent:

57940029, Aug 11, 1998

Filed:

Mar 22, 1996

Appl. No.:

8/620624

Inventors:

Philip G. Rosen - El Segundo CA

Assignee:

Raytheon Company - Lexington MA

International Classification:

G06F 300

US Classification:

395381

Abstract:

A system and technique for synchronizing data to instructions. The inventive system (10) includes a processor (12), a first memory (14) for providing instructions to the processor (12), a second memory (16) for providing data to the processor (12); and a logic circuit (18, 20), responsive to the second memory (16), for synchronizing the input of instructions from the first memory (14) to the processor (12) based on the rate of flow of data into the second memory (16). In a particular implementation, the second memory (16) is a first-in, first-out (FIFO) memory which provides output data at a first output terminal and an `almost empty` output signal at a second output terminal thereof. The logic circuit includes an OR gate (18) having a first input terminal connected to the second terminal of the FIFO memory, a second input terminal connected to a source (22) of a clock signal and an output terminal. The logic circuit further includes a register (20) having a first input terminal connected to the first memory (14), an output terminal connected to the processor (12) and a clock input terminal connected to the output terminal of the OR gate (18).

US Patent:

54523230, Sep 19, 1995

Filed:

Dec 6, 1993

Appl. No.:

8/161622

Inventors:

Philip G. Rosen - El Segundo CA

Assignee:

Hughes Aircraft Company - Los Angeles CA

International Classification:

H04L 702
H03K 5135

US Classification:

375354

Abstract:

A data synchronizer (10) for synchronizing data generated by a data source (16) at a first rate includes a first timer (22) for generating a first timing signal at the first rate. A first register (20) connected to the first timer (22) has an input connected to the data source (16). The first register (20) temporarily stores multi-bit data words from the date source (16). A second timer (26) generates a second timing signal at the second rate. A second register (24) connected to the second timer (26) has an input connected to an output of the first register (20). The second register (24) temporarily stores multi-bit data words from the first register (20). A synchronizer connected to the first and second timers (22, 26) generates a good data signal when the multi-bit data words from the first register (20) is available at an output of the second register (24).

US Patent:

58322914, Nov 3, 1998

Filed:

Dec 15, 1995

Appl. No.:

8/572932

Inventors:

Philip G. Rosen - El Segundo CA
Krzysztof W. Przytula - Santa Monica CA
David A. Schwartz - Moorpark CA

Assignee:

Raytheon Company - Lexington MA

International Classification:

G06F 1300

US Classification:

39580011

Abstract:

A data processor intended for a single instruction, multiple data mode operation includes memory that is external to the processor array, and a controller that dynamically and selectably interconnects multiple edges of the processor array with the memory and with I/O ports. A separate controller module is provided for each memory channel, and interconnects with corresponding edge processing elements of the processor array. The controller modules for the different channels are independent of each other, as are the channel memories. In the case of a rectangular processor array, each channel memory can be implemented with only three memory stores that are interconnected with the four edges of the processing array and the I/O ports through the channel controller module, yet for most algorithms provide a throughput that is comparable to that resulting from the use of four memory stores.