Philip L Flaitz

US Patent:

6410399, Jun 25, 2002

Filed:

Jun 29, 2000

Appl. No.:

09/606493

Inventors:

Philip Lee Flaitz - Newburgh NY
Herbert L. Ho - Cornwall NY
Subramanian Iyer - Mount Kisco NY
Babar Khan - Ossining NY
Paul C. Parries - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2120

US Classification:

438387, 438241, 438243

Abstract:

A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.

US Patent:

6707086, Mar 16, 2004

Filed:

Jun 15, 2000

Appl. No.:

09/594638

Inventors:

Rajarao Jammy - Wappingers Falls NY
Philip L. Flaitz - Newburgh NY
Philip E. Batson - Katonah NY
Hua Shen - Beacon NY
Yun Yu Wang - Poughquah NY

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corp. - Armonk NY

International Classification:

H01L 31119

US Classification:

257296, 257301, 257309

Abstract:

In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed surface, precleaning the exposed surface by employing a hydrogen prebake and exposing the exposed surface to nitrogen to form a crystalline silicon nitride layer. Also, a trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surface substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the sidewalls of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.

US Patent:

6740568, May 25, 2004

Filed:

Jul 29, 2002

Appl. No.:

10/206875

Inventors:

Yun Yu Wang - Poughquag NY
Johnathan Faltermeier - LaGrange NY
Colleen M. Snavely - Hopewell Junction NY
Michael Maldei - Durham NC
Michael M. Iwatake - Wappingers Falls NY
David M. Dobuzinsky - New Windsor NY
Ravikumar Ramachandran - Pleasantville NY
Viraj Y. Sardesai - Poughkeepsie NY
Philip L. Flaitz - Newburgh NY
Lisa Y. Ninomiya - Danbury CT

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H01L 2136

US Classification:

438486, 438300, 438413, 438481, 438482, 438607, 438250, 438253, 438393, 438396

Abstract:

In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.

US Patent:

6746933, Jun 8, 2004

Filed:

Oct 26, 2001

Appl. No.:

09/999803

Inventors:

Jochen Beintner - Wappingers Falls NY
Rama Divakaruni - Ossining NY
Johnathan Faltermeier - Lagrange NY
Philip L. Flaitz - Newburgh NY
Oleg Gluschenkov - Wappingers Falls NY
Carol J. Heenan - LaGrangeville NY
Rajarao Jammy - Wappingers Falls NY
Byeong Kim - Lagrangeville NY
Mihel Seitz - Wappingers Falls NY
Akira Sudo - Yokohama, JP
Yoichi Takegawa - Yokohama, JP

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21762

US Classification:

438424

Abstract:

An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

US Patent:

6960514, Nov 1, 2005

Filed:

Mar 18, 2004

Appl. No.:

10/803395

Inventors:

Jochen Beintner - Wappingers Falls NY, US
Rama Divakaruni - Ossining NY, US
Johnathan Faltermeier - Lagrange NY, US
Philip L. Flaitz - Newburgh NY, US
Oleg Gluschenkov - Wappingers Falls NY, US
Carol J. Heenan - Lagrangeville NY, US
Rajarao Jammy - Wappingers Falls NY, US
Byeong Kim - Lagrangeville NY, US
Mihel Seitz - Wappingers Falls NY, US
Akira Sudo - Yokohama, JP
Yoichi Takegawa - Yokohama, JP

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/762

US Classification:

438424, 438701

Abstract:

An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

US Patent:

7102232, Sep 5, 2006

Filed:

Apr 19, 2004

Appl. No.:

10/827693

Inventors:

Lawrence A. Clevenger - LaGrangeville NY, US
Stefanie R. Chiras - Peekskill NY, US
Timothy Dalton - Ridgefield CT, US
James J. Demarest - Fishkill NY, US
Derren N. Dunn - Fishkill NY, US
Chester T. Dziobkowski - Hopewell Junction NY, US
Philip L. Flaitz - Newburgh NY, US
Michael W. Lane - Cortlandt Manor NY, US
James R. Lloyd - Katonah NY, US
Darryl D. Restaino - Modena NY, US
Thomas M. Shaw - Peekskill NY, US
Yun-Yu Wang - Poughquag NY, US
Chih-Chao Yang - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/52

US Classification:

257751, 257758, 257753, 257E2316, 257E21584

Abstract:

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

US Patent:

7402532, Jul 22, 2008

Filed:

Aug 4, 2006

Appl. No.:

11/499220

Inventors:

Lawrence A. Clevenger - LaGrangeville NY, US
Stefanie R. Chiras - Peekskill NY, US
Timothy Dalton - Ridgefield CT, US
James J. Demarest - Fishkill NY, US
Derren N. Dunn - Fishkill NY, US
Chester T. Dziobkowski - Hopewell Junction NY, US
Philip L. Flaitz - Newburgh NY, US
Michael W. Lane - Cortlandt Manor NY, US
James R. Lloyd - Katonah NY, US
Darryl D. Restaino - Modena NY, US
Thomas M. Shaw - Peekskill NY, US
Yun-Yu Wang - Poughquag NY, US
Chih-Chao Yang - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48

US Classification:

438783, 257E21576

Abstract:

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

US Patent:

7820559, Oct 26, 2010

Filed:

Jun 23, 2008

Appl. No.:

12/143917

Inventors:

Lawrence A. Clevenger - LaGrangeville NY, US
Stefanie R. Chiras - Peekskill NY, US
Timothy Dalton - Ridgefield CT, US
James J. Demarest - Fishkill NY, US
Darren N. Dunn - Fishkill NY, US
Chester T. Dziobkowski - Hopewell Junction NY, US
Philip L. Flaitz - Newburgh NY, US
Michael W. Lane - Cortlandt Manor NY, US
James R. Lloyd - Katonah NY, US
Darryl D. Restaino - Modena NY, US
Thomas M. Shaw - Peekskill NY, US
Yun-Yu Wang - Poughquag NY, US
Chih-Chao Yang - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/31
H01L 21/4763

US Classification:

438783, 438654, 257E21576

Abstract:

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.