Peter J Burke

US Patent:

7531442, May 12, 2009

Filed:

Nov 30, 2005

Appl. No.:

11/290087

Inventors:

Jayanthi Pallinti - Santa Clara CA, US
Dilip Vijay - Redwood City CA, US
Hemanshu Bhatt - Vancouver WA, US
Hong Ying - Cupertino CA, US
Chiyi Kao - San Jose CA, US
Peter Burke - Portland OR, US
Ramaswamy Ranganathan - Saratoga CA, US
Qwai Low - Cupertino CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/44

US Classification:

438613, 438614, 438637, 438666

Abstract:

Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.

US Patent:

8076779, Dec 13, 2011

Filed:

Nov 8, 2005

Appl. No.:

11/269275

Inventors:

Jayanthi Pallinti - Santa Clara CA, US
Dilip Vijay - Redwood City CA, US
Hemanshu Bhatt - Vancouver WA, US
Hong Ying - Cupertino CA, US
Chiyi Kao - San Jose CA, US
Peter Burke - Portland OR, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257758, 257734, 257751, 257774, 257775, 257E25029, 257E25011, 257E23073, 257E23025, 257E23024, 257E23021, 257E21508

Abstract:

A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1. 2 μm aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0. 6 μm. Another possibility is provide an extra 0. 6 μm aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0. 6 μm aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0. 6 μm and another barrier layer of 60 nm.

US Patent:

20060237799, Oct 26, 2006

Filed:

Apr 21, 2005

Appl. No.:

11/112768

Inventors:

Hongquiang Lu - Fremont CA, US
Peter Burke - Portland OR, US
Wilbur Catabay - Saratoga CA, US

International Classification:

H01L 29/76
H01L 29/94

US Classification:

257382000

Abstract:

The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

US Patent:

20090256217, Oct 15, 2009

Filed:

Apr 14, 2008

Appl. No.:

12/102700

Inventors:

Hongquiang Lu - Fremont CA, US
Peter A. Burke - Portland OR, US
Wilbur Catabay - Saratoga CA, US

Assignee:

LSI LOGIC CORPORATION - Milpitas CA

International Classification:

H01L 27/00
H01L 21/02

US Classification:

257415, 438 50

Abstract:

The present invention is directed to structures and methods of fabricating nanotube electromechanical memory cells having a bottom electrode with a substantially planar contact surface. The bottom electrode is configured so that during the operation of the memory cell the nanotube crossbar of the cell can make contact with a substantially planar surface of the bottom electrode.

US Patent:

59168552, Jun 29, 1999

Filed:

Mar 26, 1997

Appl. No.:

8/829704

Inventors:

Steven C. Avanzino - Cupertino CA
Christy Mei-Chu Woo - Cupertino CA
Diana Marie Schonauer - San Jose CA
Peter Austin Burke - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213105
H01L 21306

US Classification:

51307

Abstract:

A polishing slurry composition and its method of making for planarization of silicon semiconductor wafers by chemical mechanical polishing of the wafer. A slurry formulation utilizing a ferric salt tungsten oxidizer, an ammonium persulfate titanium oxidizer, a fatty acid suspension agent, alumina particles with a small diameter and tight diameter range, coated with a solubility coating, and a chemical stabilizer, provides high tungsten and titanium polish rates with high selectivity to silicon dioxide, and good oxide defectivity for use in tungsten local interconnect applications. A method for making a tungsten slurry includes first thoroughly blending small diameter alumina particles with a tight diameter range in an aqueous concentrate with a suspension agent, then mixing with water and oxidizers. Ferric salt tungsten slurries made by this method provide excellent tungsten polish characteristics for via plug and local interconnect applications.