Pete M Hippleheuser from 521 Lochwood Dr, Plano, TX 75094, age 61, Phone: 972 516-9733

Us Patents

Write Merging On Stores With Different Privilege Levels
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US Patent:

20220309004, Sep 29, 2022
Filed:

Jun 16, 2022
Appl. No.:

17/842257
Inventors:

- Dallas TX, US
Timothy David ANDERSON - University Park TX, US
Pete HIPPLEHEUSER - Murphy TX, US
International Classification:

G06F 12/0888
G11C 7/10
G06F 12/0817
G06F 12/0895
G06F 12/0815
G06F 12/02
G11C 29/42
G06F 12/121
G11C 5/06
G06F 11/10
G06F 13/16
G06F 9/30
G06F 9/54
G06F 12/0806
G06F 12/0853
G06F 12/0855
G06F 12/0864
G06F 12/0891
G06F 12/128
G06F 12/0802
G06F 12/0804
G06F 12/0897
G06F 12/12
G06F 15/80
G11C 7/22
G11C 29/44
G06F 12/0811
G06F 12/0884
Abstract:

A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

Victim Cache With Write Miss Merging
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US Patent:

20220292023, Sep 15, 2022
Filed:

May 31, 2022
Appl. No.:

17/828189
Inventors:

- Dallas TX, US
Timothy David ANDERSON - University Park TX, US
Pete HIPPLEHEUSER - Murphy TX, US
International Classification:

G06F 12/0888
G06F 12/0891
G06F 9/54
G06F 12/02
G06F 12/0811
G06F 12/128
G06F 12/0817
G06F 12/0804
G06F 9/30
G11C 7/10
G11C 29/42
G11C 29/44
G06F 11/10
G06F 12/0855
G06F 12/12
G06F 12/0806
G06F 12/0815
G06F 12/0853
G06F 13/16
G06F 12/121
G06F 12/0884
G06F 12/0897
G06F 12/0895
G06F 12/0864
G11C 7/22
G11C 5/06
G06F 15/80
G06F 12/0802
Abstract:

A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

Write Merging On Stores With Different Tags
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US Patent:

20220276965, Sep 1, 2022
Filed:

May 16, 2022
Appl. No.:

17/744810
Inventors:

- Dallas TX, US
Timothy David ANDERSON - University Park TX, US
Pete HIPPLEHEUSER - Murphy TX, US
International Classification:

G06F 12/0888
G06F 12/0891
G06F 9/54
G06F 12/02
G06F 12/0811
G06F 12/128
G06F 12/0817
G06F 12/0804
G06F 9/30
G11C 7/10
G11C 29/42
G11C 29/44
G06F 11/10
G06F 12/0855
G06F 12/12
G06F 12/0806
G06F 12/0815
G06F 12/0853
G06F 13/16
G06F 12/121
G06F 12/0884
G06F 12/0897
G06F 12/0895
G06F 12/0864
G11C 7/22
G11C 5/06
G06F 15/80
G06F 12/0802
Abstract:

Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

Methods And Apparatus For Multi-Banked Victim Cache With Dual Datapath
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US Patent:

20220206949, Jun 30, 2022
Filed:

Mar 14, 2022
Appl. No.:

17/693581
Inventors:

- Dallas TX, US
Timothy David Anderson - University Park TX, US
Pete Michael Hippleheuser - Murphy TX, US
International Classification:

G06F 12/0888
G06F 12/0891
G06F 9/54
G06F 12/02
G06F 12/0811
G06F 12/128
G06F 12/0817
G06F 12/0804
G06F 9/30
G11C 7/10
G11C 29/42
G11C 29/44
G06F 11/10
G06F 12/0855
G06F 12/12
G06F 12/0806
G06F 12/0815
G06F 12/0853
G06F 13/16
G06F 12/121
G06F 12/0884
G06F 12/0897
G06F 12/0895
G06F 12/0864
G11C 7/22
G11C 5/06
G06F 15/80
G06F 12/0802
Abstract:

Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

Atomic Operations And Histogram Operations In A Cache Pipeline
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US Patent:

20230108306, Apr 6, 2023
Filed:

Nov 22, 2022
Appl. No.:

17/991926
Inventors:

- Dallas TX, US
Timothy David Anderson - University Park TX, US
Pete Michael Hippleheuser - Murphy TX, US
International Classification:

G06F 12/0888
G06F 12/0891
G06F 9/54
G06F 12/02
G06F 12/0811
G06F 12/128
G06F 12/0817
G06F 12/0804
G06F 9/30
G11C 7/10
G11C 29/42
G11C 29/44
G06F 11/10
G06F 12/0855
G06F 12/12
G06F 12/0806
G06F 12/0815
G06F 12/0853
G06F 13/16
G06F 12/121
G06F 12/0884
G06F 12/0897
G06F 12/0895
G06F 12/0864
G11C 7/22
G11C 5/06
G06F 15/80
G06F 12/0802
Abstract:

Methods, apparatus, systems and articles of manufacture to facilitate an atomic operation and/or a histogram operation in cache pipeline are disclosed An example system includes a cache storage coupled to an arithmetic component; and a cache controller coupled to the cache storage, wherein the cache controller is operable to: receive a memory operation that specifies a set of data; retrieve the set of data from the cache storage; utilize the arithmetic component to determine a set of counts of respective values in the set of data; generate a vector representing the set of counts; and provide the vector.

Methods And Apparatus For Allocation In A Victim Cache System
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US Patent:

20230032348, Feb 2, 2023
Filed:

Sep 30, 2022
Appl. No.:

17/956960
Inventors:

- Dallas TX, US
Timothy David Anderson - University Park TX, US
Pete Michael Hippleheuser - Murphy TX, US
International Classification:

G06F 12/0888
G06F 12/0891
G06F 9/54
G06F 12/02
G06F 12/0811
G06F 12/128
G06F 12/0817
G06F 12/0804
G06F 9/30
G11C 7/10
G11C 29/42
G11C 29/44
G06F 11/10
G06F 12/0855
G06F 12/12
G06F 12/0806
G06F 12/0815
G06F 12/0853
G06F 13/16
G06F 12/121
G06F 12/0884
G06F 12/0897
G06F 12/0895
G06F 12/0864
G11C 7/22
G11C 5/06
G06F 15/80
G06F 12/0802
Abstract:

Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Aggressive Write Flush Scheme For A Victim Cache
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US Patent:

20230004500, Jan 5, 2023
Filed:

Sep 9, 2022
Appl. No.:

17/941587
Inventors:

- Dallas TX, US
Timothy David ANDERSON - University Park TX, US
Pete HIPPLEHEUSER - Murphy TX, US
International Classification:

G06F 12/0888
G06F 12/0891
G06F 9/54
G06F 12/02
G06F 12/0811
G06F 12/128
G06F 12/0817
G06F 12/0804
G06F 9/30
G11C 7/10
G11C 29/42
G11C 29/44
G06F 11/10
G06F 12/0855
G06F 12/12
G06F 12/0806
G06F 12/0815
G06F 12/0853
G06F 13/16
G06F 12/121
G06F 12/0884
G06F 12/0897
G06F 12/0895
G06F 12/0864
G11C 7/22
G11C 5/06
G06F 15/80
G06F 12/0802
Abstract:

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

Methods And Apparatus To Facilitate Atomic Compare And Swap In Cache For A Coherent Level 1 Data Cache System
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US Patent:

20210406190, Dec 30, 2021
Filed:

Sep 13, 2021
Appl. No.:

17/472811
Inventors:

- Dallas TX, US
Timothy David Anderson - University Park TX, US
Pete Michael Hippleheuser - Murphy TX, US
International Classification:

G06F 12/0888
G06F 12/0891
G06F 9/54
G06F 12/02
G06F 12/0811
G06F 12/128
G06F 12/0817
G06F 12/0804
G06F 9/30
G11C 7/10
G11C 29/42
G11C 29/44
G06F 11/10
G06F 12/0855
G06F 12/12
G06F 12/0806
G06F 12/0815
G06F 12/0853
G06F 13/16
G06F 12/121
G06F 12/0884
G06F 12/0897
G06F 12/0895
G06F 12/0864
G11C 7/22
G11C 5/06
Abstract:

Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.