Paul Joseph Marcoux

Author:

Paul Marcoux

ISBN #:

2227318007

US Patent:

6857113, Feb 15, 2005

Filed:

Sep 11, 2002

Appl. No.:

10/241623

Inventors:

Jason T Gentry - Wellington CO, US
David D. Balhiser - Fort Collins CO, US
Ronald G Harber - Loveland CO, US
Bryan Haskin - Ft. Collins CO, US
Gayvin E Stong - Fort Collins CO, US
Paul J. Marcoux - Fort Collins CO, US

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F017/50
G06F019/00
G06F017/11

US Classification:

716 5, 716703, 716 15

Abstract:

A method and system of identifying one or more nets in a digital IC design that are at risk of electromigration comprises selecting a manufacturing process for the digital IC design and obtaining a clock period and process voltage. A voltage waveform transition time and effective capacitance is calculated for one or more of the nets. A maximum allowable effective capacitance for each one of the nets is calculated based upon a peak current analysis or an RMS current analysis. The effective capacitance for each net is compared against the maximum allowable capacitance to identify those nets that are at risk of failure due to the effects of electromigration.

US Patent:

48106640, Mar 7, 1989

Filed:

Aug 14, 1986

Appl. No.:

6/896560

Inventors:

Theodore I. Kamins - Palo Alto CA
Jean-Pierre Colinge - Palo Alto CA
Paul J. Marcoux - Mountain View CA
Lynn M. Roylance - Los Altos CA
John L. Moll - Palo Alto CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 2176
H01L 21265

US Classification:

437 26

Abstract:

A method for producing buried oxide layers in selected portions of a semiconductor substrate including the steps of applying a patterned mask made from a high-density material over a semiconductor substrate and selectively forming buried oxide layers by oxygen ion implantation. The high-density material of the mask is preferably tungsten, but can also be made from other suitable materials such as silicon nitride. A MOS transistor is made by the process of the present invention by applying the high-density mask material over the gate of the transistor, and forming buried oxide layers by ion implantation beneath only the source region and drain region of the transistor. The completed MOS transistor has the characteristics of reduced drain and source capacitance, reduced leakage, and faster response, but does not suffer from the floating-body effect of MOS transistors made by SOI processes.

US Patent:

45754020, Mar 11, 1986

Filed:

Feb 13, 1985

Appl. No.:

6/701270

Inventors:

Paul J. Marcoux - Mountain View CA
Eileen M. Murray - Yokohama, JP
Hugh R. Grinolds - Yokohama, JP

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

B44C 122
C03C 1300
C03C 2506
C23F 102

US Classification:

156643

Abstract:

A technique of patterning a conductive layer for interconnections in integrated circuits is disclosed. The technique enables fine line conductors to be fabricated. In accordance with the invention, a pattern for the conductors is etched into the surface of a substrate through the use of a patterned photoresist layer. The conductive layer is then deposited over the photoresist layer and into the pattern etched into the substrate surface. In intervening steps, only the portions of the conductive layer outside the depression of the pattern in the surface are removed; the portions of the conductive layer within the depression remains intact to provide the pattern of fine line conductors desired.