Paul R Malnati

US Patent:

42453070, Jan 13, 1981

Filed:

Sep 14, 1979

Appl. No.:

6/075419

Inventors:

Charles L. Kapeghian - Vincentown NJ
Charles C. Garman - Palmyra NJ
Paul R. Malnati - Delran NJ

Assignee:

Formation, Inc. - Mount Laurel NJ

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A controller for at least one secondary storage device for use in a data processing system having a system bus which accommodates a device or a CPU that first acquires control, a device bus that has the same address, data and control format as the system bus and a cache bus which maintains its own timing for address and data signals. The controller has means for transferring the control signals between the device bus and the system bus to establish control over the system bus by the secondary storage device. The data, address and control signals are transferred between the device bus and the cache bus in accordance with the cache bus timing.

US Patent:

44532113, Jun 5, 1984

Filed:

Apr 28, 1981

Appl. No.:

6/258514

Inventors:

Martin Askinazi - Dresher PA
Liam McManus - Willingboro NJ
Paul R. Malnati - Delran NJ
Charles L. Kapeghian - Vincentown NJ

Assignee:

Formation, Inc. - Mt. Laurel NJ

International Classification:

G06F 1516

US Classification:

364200

Abstract:

A single synchronous system bus interconnecting a number of distributed processors which emulate multiple channels of a multichannel system. The system uses multichannel software and each channel is distributed among all of the distributed processors. The bus provides for communication among the distributed processors and a memory controller. One of the distributed processors accepts and converts multichannel software and transmits formatted words on the system bus and another of the distributed processor stores the instruction received in the formatted words. The first processor, thereby, acquires control over the system bus and the second processor, as slave, processes the instruction received in accordance with its microde programming, generates data transfer control signals and transmits formatted words via the system bus destined for a distributed processor or main memory controller. The processor which transmitted the formatted words to a destination device relinquishes control of the system bus and the destination device acquires control of the system bus for processing the words transmitted to it.