Paul Willard Ackmann

US Patent:

6405144, Jun 11, 2002

Filed:

Jan 18, 2000

Appl. No.:

09/484602

Inventors:

Anthony J. Toprac - Austin TX
Paul Ackmann - Buda TX
Stuart E. Brown - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G01R 3126

US Classification:

702 84, 438 14, 700121

Abstract:

The present invention provides for a method and an apparatus for implementing programmed latency for improved wafer-to-wafer uniformity. Semiconductor devices for wafer-by-wafer analysis are identified. At least one value of a controlled variable in the wafer-by-wafer analysis is identified. A trajectory of recipes for the identified semiconductor devices is created. A sequence analysis of wafer-to-wafer variations is performed using the trajectory of recipes upon the identified semiconductor devices. A latency control is performed in response to the sequence analysis. A feed-forward implementation of wafer-by-wafer latency control is performed using the trajectory of recipes upon the identified semiconductor devices.

US Patent:

8010915, Aug 30, 2011

Filed:

Jul 10, 2008

Appl. No.:

12/170988

Inventors:

Norman Shaowen Chen - Poughkeepsie NY, US
Scott Goad - Pflugerville TX, US
Paul Willard Ackmann - Lakeway TX, US

Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

G06F 17/50

US Classification:

716 53, 716 55

Abstract:

An optical proximity correction (OPC) method for photolithography applications can be utilized to reduce the processing time, cost, and post-OPC file size associated with conventional methods. The OPC method provides a target layout pattern that represents a corresponding mask pattern for a photolithography mask, and aligns the target layout pattern relative to a suitably dimensioned fragmentation grid. Then, at least one feature of the target layout pattern is fragmented using the fragmentation grid. Thereafter, a fragment data set is generated in response to the grid-based fragmentation of the target layout pattern.

US Patent:

62079662, Mar 27, 2001

Filed:

Dec 4, 1998

Appl. No.:

9/205010

Inventors:

Khanh B. Nguyen - San Mateo CA
Harry Levinson - Saratoga CA
Richard D. Edwards - Austin TX
Stuart Brown - Austin TX
Paul W. Ackmann - Buda TX

Assignee:

Advanced Micro Devices, Inc - Sunnyvale CA

International Classification:

G01B11/00
7
H01L21/70

US Classification:

250548

Abstract:

An alignment mark protection structure (95) is disclosed which is used to ensure an integrity of an alignment scheme for a substrate (50) which is to be subjected to lithographic processing. The alignment mark protection structure (95) comprises the substrate (50) and an alignment mark (52) associated with the substrate (50). The alignment mark (52) reflects an alignment light (208) which is then used to determine an optimum alignment between the substrate (50) and a lithographic mask (214). A cap (100) overlies the alignment mark (52) and is substantially transparent with respect to the alignment light (208). The cap (100) protects the underlying alignment mark (52) from lithographic process-induced damage during processing and thus reduces alignment light noise, thereby improving the alignment between a mask (214) and the substrate (50) and minimizing the registration error associated with overlying layers formed on the substrate (50).

US Patent:

62716026, Aug 7, 2001

Filed:

Aug 31, 1999

Appl. No.:

9/386861

Inventors:

Paul W. Ackmann - Buda TX
Richard D. Edwards - Austin TX
Stuart E. Brown - Austin TX
Khanh B. Nguyen - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 23544

US Classification:

257797

Abstract:

A method for processing a semiconductor substrate is presented wherein an alignment mark is formed in an alignment mark area of the semiconductor substrate. The alignment mark area is contained within a window area of the semiconductor substrate. The upper surface of the semiconductor substrate within the window area is recessed below the upper surface of the semiconductor substrate outside of the window area, preferably by exposing the upper surface of the semiconductor substrate within the window area to an etchant. Such recession forms an alignment mark trench within the window area. Being substantially recessed below the original surface of the semiconductor substrate, an alignment mark formed in such a manner may be substantially protected from chemical-mechanical polishing damage during subsequent processing steps.

US Patent:

57576734, May 26, 1998

Filed:

Oct 10, 1996

Appl. No.:

8/728207

Inventors:

Paul Ackmann - Buda TX
Stu Brown - Austin TX
Richard Edwards - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 1760

US Classification:

364552

Abstract:

An automated data management system for enabling the analysis and control of the performance of photolithography steppers in a submicron fabrication facility disclosed. In a preferred embodiments, software running on each of a plurality of first personal computers (PCs), each of which is connected to one of a plurality of steppers, is used to append printer data generated by the steppers responsive to tests, performed therein to ASCII files associated with the steppers and subsequently to upload the ASCII files to a network drive at specified time intervals. Once the ASCII files have been uploaded to the VAX drive, the files may be accessed by a user outside the facility using a second PC on which is running a utility of the present invention for providing automated analysis of the data for a particular stepper as requested by a user. In one aspect of the invention, the utility of the present invention comprises a windows-based user interface for enabling the user to select and initiate analysis procedures by selecting from a variety of options displayed on the user's PC. In another aspect of the invention, the utility of the present invention enables the user to select from among a variety of formats, including browse tables, charts and graphs, for viewing the resulting analysis data.

US Patent:

61782564, Jan 23, 2001

Filed:

Dec 1, 1998

Appl. No.:

9/201937

Inventors:

Khanh B. Nguyen - San Mateo CA
Paul W. Ackmann - Buda TX
Stuart Brown - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06K 900

US Classification:

382144

Abstract:

A method (200) of characterizing a lithographic printer includes the steps of printing a first and second pattern (202, 228) on substrates (214) using a reticle (220) having a first and second orientation. The method (200) further includes measuring a critical dimension of the first and second pattens at two points (230, 234) and determining an imaging system component of the critical dimension of the patterns at the two points (236). The method (200) may be further expanded to encompass substantially all the points within the image field.

US Patent:

55860591, Dec 17, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/476937

Inventors:

Anastasia L. Oshelski - Austin TX
Paul Ackmann - Buda TX
Stu Brown - Austin TX
Richard Edwards - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 1760

US Classification:

364552

Abstract:

An automated data management system for enabling the analysis and control of the performance of photolithography steppers in a submicron fabrication facility is disclosed. In a preferred embodiments, software running on each of a plurality of first personal computers (PCs), each of which is connected to one of a plurality of steppers, is used to append printer data generated by the steppers responsive to tests performed therein to ASCII files associated with the steppers and subsequently to upload the ASCII files to a network drive at specified time intervals. Once the ASCII files have been uploaded to the VAX drive, the files may be accessed by a user outside the facility using a second PC on which is running a utility of the present invention for providing automated analysis of the data for a particular stepper as requested by a user. In one aspect of the invention, the utility of the present invention comprises a windows-based user interface for enabling the user to select and initiate analysis procedures by selecting from a variety of options displayed on the user's PC. In another aspect of the invention, the utility of the present invention enables the user to select from among a variety of formats, including browse tables, charts and graphs, for viewing the resulting analysis data.

US Patent:

20210134658, May 6, 2021

Filed:

Jan 11, 2021

Appl. No.:

17/145555

Inventors:

- Santa Clara CA, US
Yuping REN - Clifton Park NY, US
Paul ACKMANN - Gansevoort NY, US
Guoxiang NING - Clifton Park NY, US

International Classification:

H01L 21/768
H01L 21/027
H01L 21/283
H01L 21/311

Abstract:

The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.