Patrick R Schaumont

US Patent:

20070038867, Feb 15, 2007

Filed:

Jun 2, 2004

Appl. No.:

10/554763

Inventors:

Ingrid Verbauwhede - Palo Alto CA, US
Patrick Schaumont - Blacksburg VA, US
David Hwang - Irvine CA, US
Shenglin Yang - Boise ID, US
Kazuo Sakiyama - Leuven-Heverlee, BE
Yi Fan - Valencia CA, US
Alireza Hodjat - Santa Monica CA, US

International Classification:

H04K 1/00

US Classification:

713186000

Abstract:

A secure embedded system that uses cryptographic and biometric signal processing acceleration is described. In one embodiment, the secure embedded system is configured as a wireless pay-point protocol for brick-and-mortar and e-commerce applications in which biometric information is localized and does not require transmission of biometric data for authentication. In one embodiment, a key-generation function uses a dynamic key generator and static biometric components. In one embodiment, an embedded system design methodology provides hardware and software acceleration transparency.

US Patent:

20080012688, Jan 17, 2008

Filed:

Jul 5, 2007

Appl. No.:

11/773734

Inventors:

Dong Ha - Blacksburg VA, US
Patrick Schaumont - Blacksburg VA, US

International Classification:

H04Q 5/22

US Classification:

340010100, 340572100, 340010340, 375138000

Abstract:

A radio-frequency-identification (RFID) system includes an RFID tag and an RFID reader, where the RFID reader is configured to communicate with the RFID tag using time-hopped pulse-position modulation and ultra-wideband modulation. The time-hopped pulse-position modulation includes sending from the RFID tag to the RFID reader a series of pulses in time slots selected by the RFID tag through a cryptographically secure pseudo-random generator.

US Patent:

20170344438, Nov 30, 2017

Filed:

May 16, 2017

Appl. No.:

15/596876

Inventors:

- Blacksburg VA, US
Patrick R. Schaumont - Blacksburg VA, US

International Classification:

G06F 11/14
G06F 21/71

Abstract:

Aspects disclosed in the detailed description include a microprocessor fault detection and response system. The microprocessor fault detection and response system utilizes a hardware-based fault-attack aware microprocessor extension (FAME) and a software-based trap handler for detecting and responding to a fault injection on a microprocessor. Upon detecting the fault injection, the hardware FAME switches the microprocessor from a normal mode to a safe mode and instructs the microprocessor to invoke the software-based trap handler in the safe mode. The hardware-based FAME provides fault recovery information to the software-based trap handler via a fault recovery register (FRR) for restoring the microprocessor to a fault-free state. By utilizing a combination of the hardware-based FAME and the software-based trap handler, it is possible to effectively protect the microprocessor from malicious fault attacks without significantly increasing performance and area overheads.