Pamela S Gillis

US Patent:

6577156, Jun 10, 2003

Filed:

Dec 5, 2000

Appl. No.:

09/731147

Inventors:

Darren L. Anand - Essex Junction VT
John Atkinson Fifield - Underhill VT
Pamela Sue Gillis - Jericho VT
Peter O. Jakobsen - Milton VT
Douglas Wayne Kemerer - Essex Junction VT
David E. Lackey - Jericho VT
Steven Frederick Oakland - Colchester VT
Michael Richard Ouellette - Westford VT
William Robert Tonti - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 700

US Classification:

326 37, 326 39, 3652257, 365200, 36523003

Abstract:

A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

US Patent:

6656751, Dec 2, 2003

Filed:

Nov 13, 2001

Appl. No.:

09/683050

Inventors:

John E. Andersen - Essex Junction VT
Bruce M. Cowan - Essex Junction VT
Pamela S. Gillis - Jericho VT
Steven F. Oakland - Colchester VT
Michael R. Ouellette - Westford VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2100

US Classification:

438 14, 716 5, 716 7, 716 18, 716 19, 714 30, 714721, 714733, 365201

Abstract:

Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

US Patent:

6768694, Jul 27, 2004

Filed:

Oct 7, 2002

Appl. No.:

10/265591

Inventors:

Darren L. Anand - Essex Junction VT
Bruce Cowan - Essex Junction VT
Pamela S. Gillis - Jericho VT
Peter O. Jakobsen - Milton VT
Krishnendu Mondal - Burlington VT
Steven F. Oakland - Colchester VT
Michael R. Ouellette - Westford VT
Donald L. Wheater - Hinesburg VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 700

US Classification:

3652257, 365201

Abstract:

A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.

US Patent:

7010733, Mar 7, 2006

Filed:

Oct 9, 2002

Appl. No.:

10/065365

Inventors:

Robert W. Bassett - Essex Junction VT, US
Garrett S Christensen - Endicott NY, US
Michael L. Combs - Essex Junction VT, US
L. Owen Farnsworth - Lincoln VT, US
Pamela S. Gillis - Jericho NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G01R 31/02
G06F 17/50

US Classification:

714724, 324754, 716 4

Abstract:

A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used to isolate the test of internal logic to a small number of test I/O is also used to apply parametric external I/O tests to the ASIC's functional I/O. The parametric tests are banked into pin groups and applied on the same low pin count tester used for the internal logic tests.

US Patent:

7281182, Oct 9, 2007

Filed:

Feb 22, 2005

Appl. No.:

10/906481

Inventors:

Pamela S. Gillis - Jericho VT, US
David D. Litten - Jericho VT, US
Steven F. Oakland - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714726, 714 30, 714734, 714745, 702 75, 702106, 716 6

Abstract:

A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each boundary scan segment.

US Patent:

7305600, Dec 4, 2007

Filed:

Aug 29, 2003

Appl. No.:

10/651874

Inventors:

Michael Z. Felske - Milton VT, US
Pamela S. Gillis - Jericho VT, US
Benjamin P. Lynch - Colchester VT, US
Michael R. Ouellette - Westford VT, US
Thomas St.Pierre - Forstinning, DE
Tad J. Wilder - South Hero VT, US
Carl F. Barnhart - Ojai CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

An integrated circuit, including: a multiplicity of macro-circuits, each macro-circuit having the same function; a fuse bank containing a multiplicity of fuses, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

US Patent:

7478301, Jan 13, 2009

Filed:

May 2, 2008

Appl. No.:

12/114198

Inventors:

Michael Z. Felske - Milton VT, US
Pamela S. Gillis - Jericho VT, US
Benjamin P. Lynch - Colchester VT, US
Michael R. Ouellette - Westford VT, US
Thomas St. Pierre - Forstinning, DE
Tad J. Wilder - South Hero VT, US
Carl F. Barnhart - Ojai CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714729, 714726

Abstract:

An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

US Patent:

8230283, Jul 24, 2012

Filed:

Dec 18, 2009

Appl. No.:

12/641456

Inventors:

Pamela S. Gillis - Essex Junction VT, US
Vikram Iyengar - Essex Junction VT, US
Steven F. Oakland - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

714731

Abstract:

A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i. e. , shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.