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Pablo Moreno Galbis

age ~43

from Burlingame, CA

Also known as:
  • Pablo M Galbis
  • Pablo Moreno
  • Galbis Pablo Moreno
  • Pablo S

Pablo Galbis Phones & Addresses

  • Burlingame, CA
  • San Mateo, CA
  • Palo Alto, CA
  • Mountain View, CA

Work

  • Company:
    Analog devices inc.
    Jul 2007
  • Position:
    Design engineer

Education

  • Degree:
    MSEE
  • School / High School:
    Stanford University
    2005 to 2007
  • Specialities:
    MOS IC, BJT IC, MOS RFIC, VLSI Data Converters, VLSI Design

Skills

Analog Circuit Design • Analog • Rf • Electronics • Cmos • Asic • Semiconductors • Integrated Circuit Design • Antennas • Power Management • Circuit Design • Ic • Electromagnetics • Mixed Signal • Testing • Electrical Engineering • Matlab • Mobile Devices • Analog Design • Cadence • Spice • Amplifiers • High Speed Design • Lna

Languages

English • Spanish • French

Industries

Consumer Electronics

Us Patents

  • Assisting An Output Current Of A Voltage Converter

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  • US Patent:
    20120293156, Nov 22, 2012
  • Filed:
    Jun 21, 2012
  • Appl. No.:
    13/529085
  • Inventors:
    Pablo Moreno Galbis - Palo Alto CA, US
    James E.C. Brown - San Jose CA, US
  • Assignee:
    R2 SEMICONDUCTOR, INC. - Sunnyvale CA
  • International Classification:
    G05F 1/565
  • US Classification:
    323350
  • Abstract:
    Methods, apparatuses and systems for assisting an output current of a voltage converter, are disclosed. One method includes detecting a request for a positive change in an output voltage of the voltage converter, selecting an output current assist value based on the requested positive change in the output voltage, for a predetermined load, and assisting the output current with the selected output assist current.
  • Dc-Dc Converter Enabling Rapid Output Voltage Changes

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  • US Patent:
    20130249505, Sep 26, 2013
  • Filed:
    May 1, 2013
  • Appl. No.:
    13/874631
  • Inventors:
    James E.C. Brown - San Jose CA, US
    Daniel Dobkin - Sunnyvale CA, US
    Pablo Moreno Galbis - Palo Alto CA, US
    Cory Severson - Coarsegold CA, US
    David Fisher - Menlo Park CA, US
  • Assignee:
    R2 SEMICONDUCTOR, INC. - Sunnyvale CA
  • International Classification:
    G05F 3/08
  • US Classification:
    323223
  • Abstract:
    Embodiments for methods, apparatus and systems for operating a voltage regulator are disclosed. One embodiment of the voltage regulator generates a switching voltage through controlled closing and opening of a series switch element and a shunt switch element. The voltage regulator further includes a switched output filter that includes a plurality of capacitors for filtering the switching voltage and generating an output voltage. A mode controller is operative to disconnect at least one of the plurality of capacitors upon receiving a first indicator, where disconnecting causes the at least one of the plurality of capacitors to electrically float, wherein while the at least one capacitor is disconnected the output voltage is changed from a first value to a second value, return the output voltage to a first value or a third value upon receiving a second indicator, and reconnect the at least one of the plurality of capacitors.
  • Multimode Operation Dc-Dc Converter

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  • US Patent:
    20130267187, Oct 10, 2013
  • Filed:
    Jun 5, 2013
  • Appl. No.:
    13/910259
  • Inventors:
    James E.C. Brown - San Jose CA, US
    Daniel Dobkin - Sunnyvale CA, US
    Pablo Moreno Galbis - Palo Alto CA, US
    Cory Severson - Coarsegold CA, US
    Lawrence M. Burns - Los Altos CA, US
  • Assignee:
    R2 SEMICONDUCTOR, INC. - Sunnyvale CA
  • International Classification:
    H02M 3/156
  • US Classification:
    4551272, 323311
  • Abstract:
    Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One apparatus includes a switching voltage regulator, wherein the switching voltage regulator includes a series switch element, a shunt switch element, a switching controller and a switched output filter. The switching controller is configured to generate a switching voltage through controlled closing and opening of the series switch element and the shunt switch element. The switched output filter filters the switching voltage and generates a regulated output voltage, wherein the switched output filter includes a plurality of capacitors that are selectively included within the switched output filter.
  • Assisting A Load Current Of A Switching Voltage Regulator

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  • US Patent:
    20130321076, Dec 5, 2013
  • Filed:
    Jun 4, 2012
  • Appl. No.:
    13/488268
  • Inventors:
    Pablo Moreno Galbis - Palo Alto CA, US
    James E.C. Brown - San Jose CA, US
  • Assignee:
    R2 SEMICONDUCTOR, INC. - Sunnyvale CA
  • International Classification:
    H03F 3/20
    G05F 1/46
  • US Classification:
    330127, 323282, 323284
  • Abstract:
    Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One method includes generating, by a switching controller, a switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and generating an output voltage by filtering the switching voltage with an output inductor and a load capacitor. The method further includes generating an assisting current based on a value of current conducted through the output inductor, and assisting the load current by summing the assisting current with the current conducted through the inductor.
  • Suppressing Oscillations In An Output Of A Switched Power Converter

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  • US Patent:
    20140009130, Jan 9, 2014
  • Filed:
    Mar 12, 2013
  • Appl. No.:
    13/795505
  • Inventors:
    Pablo Moreno Galbis - Palo Alto CA, US
    James E. C. Brown - San Jose CA, US
    Cory Severson - Coarsegold CA, US
  • Assignee:
    R2 Semiconductor, Inc. - Sunnyvale CA
  • International Classification:
    G05F 1/46
  • US Classification:
    323271
  • Abstract:
    Embodiments of systems, methods and apparatuses of a switching voltage regulator are disclosed. One switching voltage regulator includes a series switch element, a shunt switch element, a PWM controller, and a mode controller. The PWM controller includes an error amplifier and a switching controller. The error amplifier generates an error signal based on a difference between a reference voltage and an output voltage. Further, the switching controller is operative to generate switch element control voltages based on the error signal, for controlling opening and closing of the series switch element and the shunt switch element, wherein the opening and closing of the series switch element and the shunt switch element generates a switching voltage. The mode controller is operative adjust a gain of the error amplifier over a selected range of frequencies based on a parameter indicative of a likelihood of oscillations in the output voltage.
  • Multimode Operation Dc-Dc Converter

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  • US Patent:
    20120244916, Sep 27, 2012
  • Filed:
    Feb 18, 2012
  • Appl. No.:
    13/400048
  • Inventors:
    James E. C. Brown - San Jose CA, US
    Daniel Dobkin - Sunnyvale CA, US
    Pablo Moreno Galbis - Palo Alto CA, US
    Cory Severson - Coarsegold CA, US
    Lawrence M. Burns - Los Altos CA, US
  • Assignee:
    R2 SEMICONDUCTOR, INC. - Sunnyvale CA
  • International Classification:
    H04B 1/38
    G05F 3/16
  • US Classification:
    455571, 323223
  • Abstract:
    Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One method includes generating, by a switching controller, a switching voltage through controlled closing and opening of a series switch element and a shunt switch element. Further, the method includes generating, by a switchable output filter, a regulated output voltage by filtering the switching voltage, wherein the switchable output filter comprises a plurality of capacitors that are selectively included within the switchable output filter.
  • Start-Up Speed Enhancement Circuit And Method For Lower-Power Regulators

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  • US Patent:
    20200097033, Mar 26, 2020
  • Filed:
    Sep 23, 2019
  • Appl. No.:
    16/579210
  • Inventors:
    - San Jose CA, US
    Pradeep Shettigar - San Jose CA, US
    Pablo Moreno Galbis - San Mateo CA, US
  • International Classification:
    G05F 1/56
    G05F 1/46
  • Abstract:
    A start-up speed enhancement circuit and method for lower-power regulators is provided herein. Operations of a method can comprise detecting a condition of a power regulator being a start-up condition and applying a first current and a second current to the power regulator based on the start-up condition. The method can also comprise determining the condition of the power regulator changes from the start-up condition to an operation condition. Further, the method can comprise stopping application of the second current to the power regulator based on the condition being the operation condition.
  • Reducing High-Frequency Noise In Pulse-Skipping Mode Of A Voltage Regulator

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  • US Patent:
    20140253065, Sep 11, 2014
  • Filed:
    Jul 21, 2013
  • Appl. No.:
    13/947077
  • Inventors:
    James E. C. Brown - San Jose CA, US
    Pablo Moreno Galbis - Burlingame CA, US
    John O'Boyle, III - San Francisco CA, US
  • Assignee:
    R2 SEMICONDUCTOR, INC. - Sunnyvale CA
  • International Classification:
    H02M 3/158
  • US Classification:
    323272, 323311
  • Abstract:
    Embodiments of systems, methods and apparatuses of a voltage regulator are disclosed. One apparatus of the voltage regulator includes a series switch element, wherein the series switch element comprises a plurality of partitioned series switch elements, a shunt switch element, and a switching controller. The switching controller is operative to control the series switch element and the shunt switch element in an idle state, wherein none of the plurality of partitioned series switch elements are active, control the series switch element and the shunt switch element in a burst state, wherein N of the plurality of partitioned series switch elements are active, and control the series switch element and the shunt switch element in a transition state, wherein M of the plurality of partitioned series switch elements are active, and wherein M is less than N.

Resumes

Pablo Galbis Photo 1

Analog Mixed Signal Design Engineer

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Location:
1499 Oak Grove Ave, Burlingame, CA 94010
Industry:
Consumer Electronics
Work:
Analog Devices Inc. since Jul 2007
Design Engineer

National Semiconductors Jun 2006 - Sep 2006
Design Engineer Internship

UPV / EADS Oct 2004 - Jul 2005
Junior Engineer

European Space Agency (ESTEC) Mar 2004 - Sep 2004
Intern

Autocruise / ENSTB Dec 2003 - Mar 2004
Intern
Education:
Stanford University 2005 - 2007
MSEE, MOS IC, BJT IC, MOS RFIC, VLSI Data Converters, VLSI DesignResearch: UWB Communications systems, Oversampled ADC with professor Bruce Wooley. Analog CMOS HD Video Buffer with professor Boris Murmman Projects: CMOS High-speed OTA, CMOS sub-1dB NF RF LNA, CMOS high-SNDR T&H
Ecole nationale supérieure des Télécommunications de Bretagne 2003 - 2004
RANKING: First of my year
Université de Bretagne Occidentale 2003 - 2004
DEA, Physical conception of communication systems
Universidad Politécnica de Valencia 1999 - 2004
MS, Microwave circuits and antennasRANKING: 2 out of 196
Skills:
Analog Circuit Design
Analog
Rf
Electronics
Cmos
Asic
Semiconductors
Integrated Circuit Design
Antennas
Power Management
Circuit Design
Ic
Electromagnetics
Mixed Signal
Testing
Electrical Engineering
Matlab
Mobile Devices
Analog Design
Cadence
Spice
Amplifiers
High Speed Design
Lna
Languages:
English
Spanish
French

Googleplus

Pablo Galbis Photo 2

Pablo Galbis

Education:
Luis Martínez - Enseñanza

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