Onkar S Sangha

US Patent:

20020176430, Nov 28, 2002

Filed:

Jan 25, 2001

Appl. No.:

09/770937

Inventors:

Onkar Sangha - San Jose CA, US
Ed Kwon - Fremont CA, US
Vijay Maheshwari - Fremont CA, US
Akihiro Kuichi - Saratoga CA, US

International Classification:

H04L012/56

US Classification:

370/412000, 370/395700

Abstract:

Methods and systems for managing data packets in various communication networks are provided. The system includes a first memory for storing at least a free data pointer and a buffer descriptor. The free data pointer points to a data buffer allocated in a second memory. The buffer descriptor includes at least a data pointer pointing to a data buffer configured to store one or a portion of the communication packet. The first memory has a maximum threshold such that if the number of buffer descriptors stored in the first memory reaches the maximum threshold one or more buffer descriptors stored in the first memory are transferred to the second memory.

US Patent:

20040015617, Jan 22, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/770345

Inventors:

Onkar Sangha - San Jose CA, US
Ed Kwan - Fremont CA, US

International Classification:

G06F013/00

US Classification:

710/010000

Abstract:

A network data processing system has a port that can be configured for any one of plural data formats, for example, for ATM or Frame Relay. The port configuration can be accomplished without re-manufacturing the network data processing system. The configuration can be accomplished by signals on external pins of integrated circuits forming the network processing system, and/or by software. In some embodiments, the port can be configured for any one of plural interfaces used for connection to physical layer devices, for example, UTOPIA or the serial interface. Receive and transmit clock signals can be configured to allow the receive or transmit data to be clocked on either rising or falling edges of the clock signals. Other parameters can also be configured.

US Patent:

20020138804, Sep 26, 2002

Filed:

Jan 25, 2001

Appl. No.:

09/771020

Inventors:

Onkar Sangha - San Jose CA, US
Vijay Maheshwari - Fremont CA, US

International Classification:

H03M013/00
G06F011/10
G11C029/00

US Classification:

714/758000, 714/807000

Abstract:

In order to speed up software computation of CRC, scrambler, descrambler, or other functions used to enhance reliability of data transmission, a software instruction is provided which performs a partial or complete computation of the function. A register may be provided to store a value identifying the function to be computed if multiple functions can be computed in a particular embodiment. A register can also be provided to store the number of bits on which a computation invoked by the software instruction is to be performed. Bit ordering (for example, big endian or little endian) can also be specified by a value or values stored in a register.