Ofer Shacham

US Patent:

20120324408, Dec 20, 2012

Filed:

Feb 17, 2012

Appl. No.:

13/399770

Inventors:

Ofer Shacham - Palo Alto CA, US
Mark Horowitz - Menlo Park CA, US
Stephen Richardson - Los Altos CA, US

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

G06F 17/50

US Classification:

716102

Abstract:

A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.

US Patent:

20220206796, Jun 30, 2022

Filed:

Mar 10, 2022

Appl. No.:

17/691615

Inventors:

- Mountain View CA, US
Jason Rupert Redgrave - Mountain View CA, US
Albert Meixner - Mountain View CA, US
Ofer Shacham - Los Altos CA, US

International Classification:

G06F 9/30
G06F 7/57
G06F 9/38
G06F 15/80

Abstract:

An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

US Patent:

20210004232, Jan 7, 2021

Filed:

Aug 24, 2020

Appl. No.:

17/001097

Inventors:

- Mountain View CA, US
Jason Rupert Redgrave - Mountain View CA, US
Ofer Shacham - Los Altos CA, US
Daniel Frederic Finchelstein - Redwood City CA, US
Qiuling Zhu - San Jose CA, US

International Classification:

G06F 9/38
G06T 1/20
G06F 9/30
G06F 15/80
H04N 3/14

Abstract:

An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

US Patent:

20200275040, Aug 27, 2020

Filed:

Apr 27, 2020

Appl. No.:

16/859308

Inventors:

- Mountain View CA, US
Albert Meixner - Mountain View CA, US
Qiuling Zhu - San Jose CA, US
Jason Rupert Redgrave - Mountain View CA, US
Ofer Shacham - Los Altos CA, US
Daniel Frederic Finchelstein - Redwood City CA, US

International Classification:

H04N 5/369
G06T 1/60
H04N 5/91

Abstract:

An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

US Patent:

20200186667, Jun 11, 2020

Filed:

Feb 10, 2020

Appl. No.:

16/786359

Inventors:

- Mountain View CA, US
Jason Rupert Redgrave - Mountain View CA, US
Ofer Shacham - Los Altos CA, US
Qiuling Zhu - San Jose CA, US
Daniel Frederic Finchelstein - Redwood City CA, US

International Classification:

H04N 1/32
B41F 15/08
G06T 1/60

Abstract:

A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.

US Patent:

20200167890, May 28, 2020

Filed:

Nov 25, 2019

Appl. No.:

16/694335

Inventors:

- Mountain View CA, US
Edward Chang - Saratoga CA, US
Daniel Finchelstein - Redwood City CA, US
Timothy Knight - Sunnyvale CA, US
William Mark - Mountain View CA, US
Albert Meixner - Mountain View CA, US
Shahriar Rabii - Los Altos CA, US
Jason Redgrave - Mountain View CA, US
Masumi Reynders - Cupertino CA, US
Ofer Shacham - Los Altos CA, US
Don Stark - Palo Alto CA, US
Michelle Tomasko - Los Gatos CA, US

International Classification:

G06T 1/20
G06K 9/00
H04N 5/232
H04N 5/217
G06T 3/40

Abstract:

An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.

US Patent:

20200120287, Apr 16, 2020

Filed:

Oct 22, 2019

Appl. No.:

16/659702

Inventors:

- Mountain View CA, US
Ofer Shacham - Los Altos CA, US
Jason Rupert Redgrave - Mountain View CA, US
Daniel Frederic Finchelstein - Redwood City CA, US
Albert Meixner - Mountain View CA, US

International Classification:

H04N 5/262
G06T 1/20
G06T 1/60

Abstract:

In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

US Patent:

20200020069, Jan 16, 2020

Filed:

Aug 1, 2019

Appl. No.:

16/529633

Inventors:

- Mountain View CA, US
Hyunchul Park - Santa Clara CA, US
William R. Mark - Mountain View CA, US
Daniel Frederic Finchelstein - Redwood City CA, US
Ofer Shacham - Los Altos CA, US

International Classification:

G06T 1/20
G06F 8/41
G06F 9/50

Abstract:

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for restructuring an image processing pipeline. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; or splitting the directed acyclic graph into smaller graphs.