Nikil D Dutt

US Patent:

7533294, May 12, 2009

Filed:

Sep 9, 2005

Appl. No.:

11/223784

Inventors:

Prabhat Mishra - Gainesville FL, US
Nikil Dutt - Irvine CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

G06F 11/00

US Classification:

714 10, 714 32, 708233

Abstract:

A functional coverage based test generation technique for pipelined architectures is presented. A general graph-theoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. A functional fault model is developed and used to define the functional coverage for pipelined architectures. Test generation procedures are developed that accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. A graph model of the pipelined processor is automatically generated from the specification using functional abstraction. Functional test programs are generated based on the coverage of the pipeline behavior. Module level property checking is used to reduce test generation time.

US Patent:

7778815, Aug 17, 2010

Filed:

May 26, 2005

Appl. No.:

11/139370

Inventors:

Sudeep Pasricha - Irvine CA, US
Nikil Dutt - Irvine CA, US
Mohamed Ben-Romdhane - Irvine CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

G06F 13/12

US Classification:

703 22, 703 13, 703 14, 703119, 703 20, 703 21, 716 4, 716 6

Abstract:

A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.

US Patent:

8166467, Apr 24, 2012

Filed:

Jan 11, 2007

Appl. No.:

11/651988

Inventors:

Partha Biswas - Natick MA, US
Laura Pozzi - Lugano, CH
Nikil Dutt - Irvine CA, US
Paolo Ienne - Lausanne, CH

Assignee:

Ecole Polytechnique Federale De Lausanne - Lausanne

International Classification:

G06F 9/45

US Classification:

717156, 717151, 717155

Abstract:

Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem. We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2. 8× over pure software execution. Moreover, the number of required memory-access instructions is reduced by two thirds on average, suggesting corresponding benefits on energy consumption.

US Patent:

8395408, Mar 12, 2013

Filed:

Oct 31, 2011

Appl. No.:

13/286136

Inventors:

Kazuyuki Tanimura - Irvine CA, US
Nikil Dutt - Irvine CA, US

Assignee:

Regents of The University of California - Oakland CA

International Classification:

H03K 19/00

US Classification:

326 8, 326 9, 326 10

Abstract:

Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.

US Patent:

8621444, Dec 31, 2013

Filed:

Sep 30, 2004

Appl. No.:

10/599593

Inventors:

Nikil Dutt - Irvine CA, US
Mohammad H. Reshadi - Irvine CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

G06F 9/45

US Classification:

717138, 717140, 703 26

Abstract:

Methods for simulating an instruction set architecture (ISA) with a instruction set simulator (ISS) are provided. One exemplary embodiment of the methods includes fetching a first decoded instruction during a run time, where the decoded instruction is decoded from an original instruction in a target application program during a compile time preceding the run time. The decoded instruction can designate a template configured to implement the functionality of the original instruction. The method also preferably includes determining whether the fetched instruction is modified from the original instruction and then executing the designated template if the instruction was not modified. The method can also include decoding the original instruction during the compile time by selecting a template corresponding to the original instruction and then customizing the template based on the data in original instruction. The method can also include optimizing the customized template during the compile time.

US Patent:

20050193359, Sep 1, 2005

Filed:

Feb 14, 2005

Appl. No.:

11/057416

Inventors:

Rajesh Gupta - San Diego CA, US
Sumit Gupta - Mountain View CA, US
Nikil Dutt - Irvine CA, US
Alexandru Nicolau - Irvine CA, US

International Classification:

G06F017/50

US Classification:

716018000

Abstract:

A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase for implementing the transformed behavioral description using lower level primitives, and a fourth phase for generating implementation codes for the design.

US Patent:

20130293259, Nov 7, 2013

Filed:

Mar 11, 2013

Appl. No.:

13/794775

Inventors:

Nikil Dutt - Irvine CA, US

International Classification:

H03K 19/003

US Classification:

326 8

Abstract:

Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.

US Patent:

20190343457, Nov 14, 2019

Filed:

May 8, 2019

Appl. No.:

16/406739

Inventors:

- Oakland CA, US
Nikil Dutt - Irvine CA, US
Kai Zheng - Irvine CA, US
Ariana Nelson - Orange CA, US
Pasi Liljeberg - Turku, FI
Sanna Salantera - Turku, FI
Mingzhe Jiang - Turku, FI
Arman Anzanpour - Turku, FI
Elise Syrjala - Turku, FI
Riitta Mieronkoski - Turku, FI
Geng Yang - Hangzhou, CN

International Classification:

A61B 5/00
G16H 50/30
G06N 3/08
A61B 5/0492
A61B 5/0205

Abstract:

Systems and methods for automatic pain monitoring and assessment are described herein. In one example, the system may include a wearable facial expression capturing system that is placed over a subject's face. The system may be embedded with a plurality of sensors configured to detect biosignals from facial muscles and may additionally include a sensor node that recognizes facial expressions based on the detected biosignals. Pain experienced by the subject is assessed based on the facial expressions in conjunction with physiological signals obtained by other wearable sensors.

Author:

Nikil D. Dutt

ISBN #:

0387261435

Author:

Nikil D. Dutt

ISBN #:

0792383621

Author:

Nikil Dutt

ISBN #:

0387263993