Nicholas J Foskett from 251 View St, Mountain View, CA 94041, age 64

Us Patents

Graphics Processing Unit With An Integrated Fog And Blending Operation
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US Patent:

6342888, Jan 29, 2002
Filed:

Dec 5, 2000
Appl. No.:

09/730652
Inventors:

John Erik Lindholm - Cupertino CA
Simon Moy - Mountain View CA
Kevin Dawallu - Sunnyvale CA
Mingjian Yang - Sunnyvale CA
John Montrym - Los Altos CA
David B. Kirk - San Francisco CA
Paolo E. Sabella - Pleasanton CA
Matthew N. Papakipos - Palo Alto CA
Douglas A. Voorhies - Menlo Park CA
Nicholas J. Foskett - Mountain View CA
Assignee:

nVidia Corporation - Santa Clara CA
International Classification:

G06T 1700
US Classification:

345426, 345418
Abstract:

A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for receiving vertex data. The transform module serves to transform the vertex data from a first space to a second space. Further, the transform module of the graphics pipeline system is capable of carrying out a blending operation. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. During use, the lighting module of the graphics pipeline system is capable of carrying out a fog operation.

Clipping System And Method For A Graphics Processing Framework Embodied On A Single Semiconductor Platform
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US Patent:

6462737, Oct 8, 2002
Filed:

Sep 20, 2001
Appl. No.:

09/957746
Inventors:

John Erik Lindholm - Cupertino CA
Simon Moy - Mountain View CA
Kevin Dawallu - Sunnyvale CA
Mingjian Yang - Sunnyvale CA
John Montrym - Los Altos CA
David B. Kirk - San Francisco CA
Paolo E. Sabella - Pleasanton CA
Matthew N. Papakipos - Palo Alto CA
Douglas A. Voorhies - Menlo Park CA
Nicholas J. Foskett - Mountain View CA
Assignee:

Nvidia Corporation - Santa Clara CA
International Classification:

G06T 1700
US Classification:

345426, 345418
Abstract:

A graphics pipeline system is provided with an integrated clipping operation. First included is a transform module adapted for being coupled to a buffer to receive graphics data therefrom. Such transform module is positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space. Also provided is a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module. The lighting module is adapted for performing lighting operations on the graphics data received from the transform module. A range clamp inversion function and a clipping operation are performed on the same single semiconductor platform as the transform module and the lighting module.

Method, Apparatus And Article Of Manufacture For Area Rasterization Using Sense Points
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US Patent:

6504542, Jan 7, 2003
Filed:

Dec 6, 1999
Appl. No.:

09/455305
Inventors:

Douglas A. Voorhies - Menlo Park CA
Nicholas J. Foskett - Mountain View CA
Assignee:

Nvidia Corporation - Santa Clara CA
International Classification:

G06T 1120
US Classification:

345441
Abstract:

A method, apparatus and article of manufacture are provided for performing area rasterization using sense points. Upon receipt of a primitive, e. g. a triangle, line equation coefficients of line equations are determined for lines that define the primitive. Thereafter, a plurality of points is positioned on or near the primitive. Such points define an enclosed convex region. Next, the line equations are evaluated at the points. During operation, the points and convex region are moved based on the evaluation of the line equations for the purpose of identifying an area in the primitive for rendering pixels therein.

System And Method For A Graphics Processing Framework Embodied Utilizing A Single Semiconductor Platform
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US Patent:

6577309, Jun 10, 2003
Filed:

Sep 20, 2001
Appl. No.:

09/961219
Inventors:

John Erik Lindholm - Cupertino CA
Simon Moy - Mountain View CA
Kevin Dawallu - Sunnyvale CA
Mingjian Yang - Sunnyvale CA
John Montrym - Los Altos CA
David B. Kirk - San Francisco CA
Paolo E. Sabella - Pleasanton CA
Matthew N. Papakipos - Palo Alto CA
Douglas A. Voorhies - Menlo Park CA
Nicholas J. Foskett - Mountain View CA
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06T 1700
US Classification:

345426, 345418
Abstract:

A graphics pipeline system is provided with a transform module positioned on a single semiconductor platform for transforming graphics data. Also included is a lighting module positioned on the same single semiconductor platform as the transform module for lighting the graphics data. In use, various operations may be performed utilizing the single semiconductor platform such as rendering, fog operations, blending, coloring operations, etc.

High Bandwidth-Low Latency Memory Controller
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US Patent:

6647456, Nov 11, 2003
Filed:

Feb 23, 2001
Appl. No.:

09/792874
Inventors:

James M. Van Dyke - Sunnyvale CA
Nicholas J. Foskett - Mountain View CA
Brad Simeral - San Francisco CA
Sean Treichler - Palo Alto CA
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06F 1200
US Classification:

711105, 711154, 711169
Abstract:

At memory controller system is provided including a plurality of memory controller subsystems each coupled between memory and one of a plurality of computer components. Each memory controller subsystem includes at least one queue for managing pages in the memory. In use, each memory controller subsystem is capable of being loaded from the associated computer component independent of the state of the memory. Since high bandwidth and low latency are conflicting requirements in high performance memory systems, the present invention separates references from various computer components into multiple command streams. Each stream thus can hide precharge and activate bank preparation commands within its own stream for maximum bandwidth. A page context switch technique may be employed that allows instantaneous switching from one look ahead stream to another to allow low latency and high bandwidth while preserving.

Method, Apparatus And Article Of Manufacture For Boustrophedonic Rasterization
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US Patent:

6650325, Nov 18, 2003
Filed:

Dec 6, 1999
Appl. No.:

09/454505
Inventors:

Douglas A. Voorhies - Menlo Park CA
Nicholas J. Foskett - Mountain View CA
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06T 1540
US Classification:

345426, 345422, 345428, 345581, 345586, 345552, 345561
Abstract:

A method, apparatus and article of manufacture are provided for performing rasterization using alternating sense point traversal. Upon receipt of a primitive, i. e. a triangle, a plurality of points are positioned on or near the primitive. Such points define an enclosed convex region and may be located at corners of the convex region. In operation, the points and convex region are moved in an alternating manner for the purpose of identifying an area in the primitive for rendering pixels therein. In particular, the points are moved in a boustrophedonic manner.

System, Method And Computer Program Product For Performing A Scissor Operation In A Graphics Processing Framework Embodied On A Single Semiconductor Platform
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US Patent:

6650331, Nov 18, 2003
Filed:

Sep 20, 2001
Appl. No.:

09/961228
Inventors:

John Erik Lindholm - Cupertino CA
Simon Moy - Mountain View CA
Kevin Dawallu - Sunnyvale CA
Mingjian Yang - Sunnyvale CA
John Montrym - Los Altos CA
David B. Kirk - San Francisco CA
Paolo E. Sabella - Pleasanton CA
Matthew N. Papakipos - Palo Alto CA
Douglas A. Voorhies - Menlo Park CA
Nicholas J. Foskett - Mountain View CA
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06T 1700
US Classification:

345522
Abstract:

A graphics pipeline system is provided with an integrated scissor operation. First provided is a transform module adapted for being coupled to a buffer to receive graphics data therefrom. Such transform module is positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space. Associated therewith is a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the graphics data received from the transform module. A scissor operation is performed on the same single semiconductor platform as the transform module and the lighting module.

Clip-Less Rasterization Using Line Equation-Based Traversal
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US Patent:

6765575, Jul 20, 2004
Filed:

Dec 6, 1999
Appl. No.:

09/455728
Inventors:

Douglas A. Voorhies - Menlo Park CA
Nicholas J. Foskett - Mountain View CA
Matthew N. Papakipos - Palo Alto CA
Assignee:

Nvidia Corporation - Santa Clara CA
International Classification:

G06T 1100
US Classification:

345441
Abstract:

Clip-less rasterization is provided by a plurality of operations. First, a primitive is received that is defined by a plurality of vertices. Each of such vertices includes a W-value. Thereafter, an area is identified based on the W-values. Such area is representative of a portion of a display to be drawn corresponding to the primitive.

Isbn (Books And Publications)

Conservation
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Author:

Nicholas Foskett
ISBN #:

0844226823

Leading And Managing Education: International Dimensions
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Author:

Nicholas H. Foskett
ISBN #:

0761972021

Wikipedia

Nick Foskett

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Nicholas H. "Nick" Foskett is Vice-Chancellor at Keele University in Staffordshire (August 2010- ). He was formerly a Professor of Education at the ...