Neal D Clements

US Patent:

8471606, Jun 25, 2013

Filed:

Jun 28, 2011

Appl. No.:

13/170211

Inventors:

Neal D. Clements - Fargo ND, US

Assignee:

Deere & Company - Moline IL

International Classification:

H03K 19/01
H03K 19/0175

US Classification:

327109, 327 63, 327108, 327333

Abstract:

A driver circuit for controlling a semiconductor power switch comprises a first power driver transistor and a second power driver transistor complementary to the first power driver transistor. Both power driver transistors have an output terminal connected to an input terminal of the semiconductor power switch. An input terminal of the second power driver transistor is connected to a half bridge circuit comprising a first pre-driver transistor and a second pre-driver transistor complementary to the first pre-driver transistor. Both first and second pre-driver transistors have an output terminal connected to the input terminal of the second power driver transistor. This provides fast switching times with low power consumption for the pre-driver transistors.

US Patent:

20180061570, Mar 1, 2018

Filed:

Nov 2, 2017

Appl. No.:

15/802383

Inventors:

- Moline IL, US
Neal D. Clements - Sheldon ND, US
Andrew D. Wieland - Fargo ND, US

International Classification:

H01G 2/08
H01G 4/32
H01G 4/38
H01G 4/228
H05K 1/18
H05K 1/02
H05K 3/34

Abstract:

A capacitor comprises a first winding member, where the first winding member comprises a first dielectric layer and a first conductive layer. A second winding member comprises a second dielectric layer and second conductive layer. The first winding member is interleaved, partially or entirely, with the second winding layer. A dielectric package is adapted to at least radially contain or border the first winding member and the second winding member. A first metallic member has a generally planar, radially extending surface for electrically and mechanically contacting an upper portion the first conductive layer. A second metallic member has a generally planar, radially extending surface for electrically and mechanically contacting a lower portion of the second conductive layer.

US Patent:

20170138995, May 18, 2017

Filed:

Nov 16, 2015

Appl. No.:

14/941740

Inventors:

- Moline IL, US
Neal D. Clements - Sheldon ND, US
Kent D. Wanner - Fargo ND, US

International Classification:

G01R 31/02

Abstract:

A first voltage sensor measures a primary voltage between a first terminal of a tested device and electrical ground when a first switch and a second switch are in various on states or off states. In a test state either the first switch or the second switch is in an on state and in reference state both the first switch and the second switch are in on states. An observed leakage resistance is estimated based on the measured primary and secondary voltages of the test state. A reference leakage resistance is based on the measured primary and secondary voltages of the reference state. A test circuit has failed if the observed leakage resistance differs from the reference leakage resistance by more than a threshold amount.

US Patent:

20170102437, Apr 13, 2017

Filed:

Oct 8, 2015

Appl. No.:

14/878290

Inventors:

- Moline IL, US
Neal D. CLEMENTS - Fargo ND, US
Advait DESAI - Pune, IN

International Classification:

G01R 31/40

Abstract:

In one example embodiment, a circuit includes a first sub-circuit configured to generate first data corresponding to a frequency and a duration of overloading of a transistor in the inverter, and a second sub-circuit configured to generate second data corresponding to a rate of rise of a voltage and a peak voltage value of the transistor in the inverter. The first sub-circuit and the second sub-circuit are configured to respectively provide the first data and second data as outputs to a controller for analyzing a manner in which a load coupled to the inverter is driven.

US Patent:

20160373047, Dec 22, 2016

Filed:

Aug 27, 2015

Appl. No.:

14/837496

Inventors:

- Moline IL, US
Long Wu - Fargo ND, US
Tianjun Fu - Fargo ND, US
Robert B. Shaw - Moorhead MN, US
Neal D. Clements - Sheldon ND, US

International Classification:

H02P 29/00

Abstract:

A temperature estimation module estimates each junction temperature of a corresponding semiconductor device, among a plurality of semiconductor devices, for each phase of an inverter. The temperature estimation module or the data processing system determines a hottest device with a highest junction temperature among the semiconductor devices. A thermal adjustment module or data processing system determines if the highest junction temperature parameter is less than maximum junction temperature parameter for the respective semiconductor device or deciding whether or not to adjust a duty cycle of the semiconductor devices.

US Patent:

20160242312, Aug 18, 2016

Filed:

Apr 17, 2015

Appl. No.:

14/689528

Inventors:

- Moline IL, US
Thomas Roan - Fargo ND, US
Andrew D. Wieland - Fargo ND, US
Neal D. Clements - Sheldon ND, US

International Classification:

H05K 7/20
H05K 1/18
H05K 1/11

Abstract:

An electronic assembly comprises a semiconductor device that has conductive pads on a semiconductor first side and a metallic region on a semiconductor second side opposite the first side. A lead frame provides respective separate terminals that are electrically and mechanically connected to corresponding conductive pads. A first heat sink comprises a first component having a mating side. A portion of the mating side is directly bonded with the metallic region of the semiconductor device. A circuit board has an opening for receiving the semiconductor device. The lead frame extends outward toward the circuit board or a board first side of the circuit board.

US Patent:

20160242313, Aug 18, 2016

Filed:

Apr 17, 2015

Appl. No.:

14/689445

Inventors:

- Moline IL, US
Thomas Roan - Fargo ND, US
Andrew D. Wieland - Fargo ND, US
Neal D. Clements - Sheldon ND, US

International Classification:

H05K 7/20
H05K 1/18
H05K 1/11

Abstract:

An electronic assembly comprises a semiconductor device that has conductive pads on a semiconductor first side and a metallic region on a semiconductor second side opposite the first side. A lead frame provides respective separate terminals that are electrically and mechanically connected to corresponding conductive pads. A first heat sink comprises a first component having a mating side. A portion of the mating side is directly bonded with the metallic region of the semiconductor device. A circuit board has an opening for receiving the semiconductor device. The lead frame extends outward toward the circuit board or a board first side of the circuit board.

US Patent:

20160126011, May 5, 2016

Filed:

Oct 31, 2014

Appl. No.:

14/529337

Inventors:

- Moline IL, US
Neal D. Clements - Sheldon ND, US
Andrew D. Wieland - Fargo ND, US

International Classification:

H01G 2/08
H05K 1/18
H05K 1/02
H01G 4/38

Abstract:

A capacitor comprises a first winding member, where the first winding member comprises a first dielectric layer and a first conductive layer. A second winding member comprises a second dielectric layer and second conductive layer. The first winding member is interleaved, partially or entirely, with the second winding layer. A dielectric package is adapted to at least radially contain or border the first winding member and the second winding member. A first metallic member has a generally planar, radially extending surface for electrically and mechanically contacting an upper portion the first conductive layer. A second metallic member has a generally planar, radially extending surface for electrically and mechanically contacting a lower portion of the second conductive layer.