Nathaniel C Berliner

US Patent:

20110095393, Apr 28, 2011

Filed:

Oct 22, 2009

Appl. No.:

12/603668

Inventors:

Nathaniel C. Berliner - Albany NY, US
Kangguo Cheng - Albany NY, US
Jason E. Cummings - Albany NY, US
Toshiharu Furukawa - Essex Junction VT, US
Jed H. Rankin - Essex Junction VT, US
Robert R. Robison - Essex Junction VT, US
William R. Tonti - Essex Junction VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/06
H01L 21/66
C23F 1/08

US Classification:

257506, 438 16, 15634513, 257E21529, 257E29006

Abstract:

An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.

US Patent:

20110097824, Apr 28, 2011

Filed:

Oct 22, 2009

Appl. No.:

12/603671

Inventors:

Nathaniel C. BERLINER - Albany NY, US
Kangguo CHENG - Guilderland NY, US
Toshiharu FURUKAWA - Essex Junction VT, US
William R. TONTI - Essex Junction VT, US
Douglas C. La TULIPE, Jr. - Guilderland NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/302
C23F 1/08
H01L 21/66

US Classification:

438 14, 15634515, 257E21214, 257E21529

Abstract:

A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

US Patent:

20110198756, Aug 18, 2011

Filed:

Aug 25, 2006

Appl. No.:

12/067285

Inventors:

ü Thenappan - München NJ, US
Chien-Wei Li - Vienna VA, US
David Nalewajek - West Seneca NY, US
Martin Cheney - Hamburg NY, US
Jingyu Lao - Saline MI, US
Eric Eisenbraun - Albany NY, US
Min Li - Troy MI, US
Nathaniel Berliner - Albany NY, US
Mikko Ritala - Espoo, FI
Markku Leskela - Espoo, FI
kaupo Kukli - Polva, EE
Linda Cheney - Hamburg NY, US

International Classification:

H01L 21/3205
H01L 29/43
H01L 23/48

US Classification:

257751, 438681, 257769, 257E21294, 257E2301, 257E29139

Abstract:

Vapor deposition precursors that can deposit conformal thin ruthenium films on substrates with a very high growth rate, low resistivity and low levels of carbon, oxygen and nitrogen impurities have been provided. The precursors described herein include a compound having the formula CMC′, wherein M comprises a metal or a metalloid; C comprises a substituted or unsubstituted acyclic alkene, cycloalkene or cycloalkene-like ring structure; and C′ comprises a substituted or unsubstituted acyclic alkene, cycloalkene or cycloalkene-like ring structure; wherein at least one of C and C′ further and individually is substituted with a ligand represented by the formula CH(X)R, wherein X is a N, P, or S-substituted functional group or hydroxyl, and Ris hydrogen or a hydrocarbon. Methods of production of the vapor deposition precursors and the resulting films, and uses and end uses of the vapor deposition precursors and resulting films are also described.

US Patent:

20120125538, May 24, 2012

Filed:

Jan 27, 2012

Appl. No.:

13/359970

Inventors:

Nathaniel C. BERLINER - Albany NY, US
Kangguo CHENG - Guilderland NY, US
Toshiharu FURUKAWA - Essex Junction VT, US
William R. TONTI - Essex Junction VT, US
Douglas C. La TULIPE, JR. - Guilderland NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/306

US Classification:

15634515

Abstract:

A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

US Patent:

20130052801, Feb 28, 2013

Filed:

Aug 30, 2011

Appl. No.:

13/221198

Inventors:

Nathaniel C. Berliner - Albany NY, US
Pranita Kulkarni - Slingerlands NY, US
Nicolas Loubet - Albany NY, US
Kingsuk Maitra - Guilderland NY, US
Sanjay C. Mehta - Niskayuna NY, US
Paul A. Ronsheim - Hopewell Junction NY, US
Toyoji Yamamoto - Yokohama, JP
Zhengmao Zhu - Pougkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
RENESAS ELECTRONICS AMERICA, INC. - Santa Clara CA
GLOBALFOUNDRIES - Grand Cayman
STMICROELECTRONICS, INC. - Carrollton TX

International Classification:

H01L 21/326

US Classification:

438468, 257E21327

Abstract:

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

US Patent:

20130200467, Aug 8, 2013

Filed:

Feb 7, 2012

Appl. No.:

13/367419

Inventors:

Lisa F. Edge - Albany NY, US
Nathaniel Berliner - Albany NY, US
James John Demarest - Albany NY, US
Balasubramanian S. Haran - Albany NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/088
H01L 21/28

US Classification:

257392, 438591, 438592, 257E2119, 257E2706

Abstract:

A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.

US Patent:

20130334693, Dec 19, 2013

Filed:

Jun 18, 2012

Appl. No.:

13/525401

Inventors:

Emre Alptekin - Wappingers Falls NY, US
Nathaniel Berliner - Albany NY, US
Christian Lavoie - Ossining NY, US
Kam-Leung Lee - Yorktown Heights NY, US
Ahmet Serkan Ozcan - Pleasantville NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L 23/532
H01L 21/768

US Classification:

257769, 438683, 257E23157, 257E21593

Abstract:

A method for forming a raised silicide contact, the method including depositing a layer of silicon using a gas cluster implant technique which accelerates clusters of silicon atoms causing them to penetrate a surface oxide on a top surface of the silicide; heating the silicide including the silicon layer to a temperature from about 300 C. to about 950 and holding the temperature for about 0.1 miliseconds to about 600 seconds in an inert atmosphere causing silicon from the layer of silicon to react with the remaining silicide partially formed in the silicon containing substrate; and forming a raised silicide from the layer of silicon, wherein the thickness of the raised silicide is greater than the thickness of the silicide and the raised silicide protrudes above a top surface of the silicon containing substrate.

US Patent:

20190058032, Feb 21, 2019

Filed:

Aug 15, 2018

Appl. No.:

16/103949

Inventors:

- Aliso Viejo CA, US
Bruce Odekirk - Bend OR, US
Nathaniel Berliner - Bend OR, US
Dumitru Sdrulla - Bend OR, US

International Classification:

H01L 29/06
H01L 29/16
H01L 29/872
H01L 29/66
H01L 21/02
H01L 21/265
H01L 21/324
H01L 29/45
H01L 21/04

Abstract:

A semiconductor device constituted of: a semiconductor layer; and a field layer patterned on said semiconductor layer, said field layer constituted of material having characteristics which block diffusion of mobile ions and maintain structural integrity at activation temperatures of up to 1200 degrees centigrade.