Nathan D Fontenot

US Patent:

7571286, Aug 4, 2009

Filed:

Aug 24, 2006

Appl. No.:

11/466794

Inventors:

Nathan D. Fontenot - Cedar Park TX, US
Jacob Lorien Moilanen - Austin TX, US
Joel Howard Schopp - Austin TX, US
Michael Thomas Strosaker - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133, 711141

Abstract:

A computer implemented method, data processing system, and computer program product for reducing memory traffic via detection and tracking of temporally silent stores. When a memory store, comprising an address and a data value, to a cache is detected, a determination is made that a cache line in the cache contains a same address as the address in the memory store. A determination is then made that a tentative cache line invalidate signal for the cache line was previously sent to other data processing systems in the network to tentatively invalidate the cache line. If the memory store is a temporally silent store, a cache line revalidate signal is sent to the other data processing systems to clear the tentative invalidate signal for the cache line.

US Patent:

7861038, Dec 28, 2010

Filed:

Jul 17, 2007

Appl. No.:

11/778914

Inventors:

Nathan D. Fontenot - Cedar Park TX, US
Joel Howard Schopp - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711115

Abstract:

The illustrative embodiments described herein provide an apparatus and method for managing data in a hybrid drive system. In one embodiment, a process determines whether the detachable memory contains clean data in response to identifying that a cache portion of a detachable memory is unavailable. The clean data does not require a disk to be in a spin state to be removed from the detachable memory. The process removes the clean data from the detachable memory in response to determining that the detachable memory contains the clean data. The process stores the data on the detachable memory.

US Patent:

7870370, Jan 11, 2011

Filed:

Dec 19, 2007

Appl. No.:

11/960592

Inventors:

Nathan D. Fontenot - Cedar Park TX, US
Jacob L. Moilanen - Austin TX, US
Joel H. Schopp - Austin TX, US
Michael T. Strosaker - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712227

Abstract:

Methods, apparatus, and products for determining thermal characteristics of instruction sets comprising one or more computer program instructions executed by a computer processor are disclosed that include tracking, in a performance counter, a number of classes of instructions run during execution of a plurality of instruction sets; identifying, for each instruction set, from the performance counter, a number of each class of instructions run during execution of the instruction set; and ranking the instruction sets in dependence upon the number of each class of instructions run during execution of each instruction set and a profile of thermal characteristics of classes of instructions.

US Patent:

7958381, Jun 7, 2011

Filed:

Jun 27, 2008

Appl. No.:

12/147565

Inventors:

Nathan Fontenot - Georgetown TX, US
Jacob Lorien Moilanen - Austin TX, US
Joel Howard Schopp - Austin TX, US
Michael Thomas Strosaker - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/00

US Classification:

713323, 713320, 365226

Abstract:

A method, system, and computer usable program product for energy conservation in multipath data communications are provided in the illustrative embodiments. A current utilization of each of several of I/O devices is determined. A violation determination is made whether an I/O device from the several I/O devices can be powered down without violating a rule. The I/O device is powered down responsive to the violation determination being false. A powering up determination may be made whether an additional I/O device is needed in a multipath I/O configuration. The I/O device may be located, powered up, and made available for multipath I/O configuration. A latency determination may be made whether a latency time of the I/O device can elapse before the time when the additional I/O device is needed. The powering on may occur no later than the latency time before the time the additional I/O device is needed.

US Patent:

8140817, Mar 20, 2012

Filed:

Feb 24, 2009

Appl. No.:

12/391827

Inventors:

Joel H. Schopp - Austin TX, US
Jacob L. Moilanen - Austin TX, US
Nathan D. Fontenot - Georgetown TX, US
Michael T. Strosaker - Austin TX, US
Manish Ahuja - Pflugerville TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/14

US Classification:

711173, 711147, 710260

Abstract:

A partitioned NUMA machine is managed to dynamically transform its partition layout state based on NUMA considerations. The NUMA machine includes two or more NUMA nodes that are operatively interconnected by one or more internodal communication links. Each node includes one or more CPUs and associated memory circuitry. Two or more logical partitions each comprise at a CPU and memory circuit allocation on at least one NUMA node. Each partition respectively runs at least one associated data processing application. The partitions are dynamically managed at runtime to transform the distributed data processing machine from a first partition layout state to a second partition layout state that is optimized for the data processing applications according to whether a given partition will most efficiently execute within a single NUMA node or by spanning across a node boundary. The optimization is based on access latency and bandwidth in the NUMA machine.

US Patent:

8166480, Apr 24, 2012

Filed:

Jul 29, 2008

Appl. No.:

12/181811

Inventors:

Nathan D. Fontenot - Georgetown TX, US
Jacob Lorien Moilanen - Austin TX, US
Joel Howard Schopp - Austin TX, US
Michael Thomas Strosaker - Austin TX, US
Mark Wayne VanderWiele - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

718102, 718103

Abstract:

Illustrative embodiments provide a computer implemented method, a data processing system and a computer program product for lock contention reduction. In one illustrative embodiment, the computer implemented method provides a lock to an active thread, increments a lock counter, receives a request to de-schedule the active thread, and determines whether the lock is held by the active thread. The computer implemented method, responsive to a determination that the lock is held by the active thread, adds a first pre-determined amount to a time slice of the active thread.

US Patent:

8230425, Jul 24, 2012

Filed:

Jul 30, 2007

Appl. No.:

11/830588

Inventors:

Manish Ahuja - Pflugerville TX, US
Nathan Fontenot - Cedar Park TX, US
Jacob L. Moilanen - Austin TX, US
Joel H. Schopp - Austin TX, US
Michael T. Strosaker - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46
G06F 9/455
G06F 9/44
G06F 15/76

US Classification:

718102, 718 1, 712 32, 712200

Abstract:

Methods and arrangements of assigning tasks to processors are discussed. Embodiments include transformations, code, state machines or other logic to detect an attempt to execute an instruction of a task on a processor not supporting the instruction (non-supporting processor). The method may involve selecting a processor supporting the instruction (supporting physical processor). In many embodiments, the method may include storing data about the attempt to execute the instruction and, based upon the data, making another assignment of the task to a physical processor supporting the instruction. In some embodiments, the method may include representing the instruction set of a virtual processor as the union of the instruction sets of the physical processors comprising the virtual processor and assigning a task to the virtual processor based upon the representing.

US Patent:

8285950, Oct 9, 2012

Filed:

Jun 3, 2010

Appl. No.:

12/792850

Inventors:

Nathan D. Fontenot - Georgetown TX, US
Ryan Patrick Grimm - Austin TX, US
Monty Christoph Poppe - Austin TX, US
Joel Howard Schopp - Austin TX, US
Michael Thomas Strosaker - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711154

Abstract:

A computer implemented method for managing an execution mode for a parallel processor is provided. A monitor identifies a first efficiency rate for a first contested resource of the parallel processor operating in a first operating mode. Responsive to identifying the first efficiency rate for the first contested resource, the monitor identifies whether the first efficiency rate for the contested resource of the parallel processor operating in the first operating mode exceeds a threshold. Responsive to identifying that the efficiency rate for the contested resource exceeds the threshold, an operation of the parallel processor is changed to a second operating mode.