Nathan A Clark

US Patent:

7318143, Jan 8, 2008

Filed:

Jan 28, 2005

Appl. No.:

11/044734

Inventors:

Stuart D. Biles - Cambridge, GB
Krisztian Flautner - Cambridge, GB
Scott Mahlke - Ann Arbor MI, US
Nathan Clark - Ann Arbor MI, US

Assignee:

ARM Limited - Cambridge
University of Michigan - Ann Arbor MI

International Classification:

G06F 15/80

US Classification:

712 10, 712 15

Abstract:

An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store operable to store operand values and an accelerator having a plurality of functional units. The accelerator executes a combined operation corresponding to a computational sub-graph of the separate program instructions by configuring individual ones of said plurality of functional units to perform particular processing operations associated with the combined operation. The accelerator executes the combined operation in dependence upon operand mapping data providing a mapping between operands of the combined operation and storage locations within said operand store and in dependence upon separately specified configuration data providing a mapping between the plurality of functional units and the particular processing operations. The configuration data can be re-used for different operand mappings.

US Patent:

7343482, Mar 11, 2008

Filed:

Jan 31, 2005

Appl. No.:

11/048663

Inventors:

Stuart David Biles - Cambridge, GB
Krisztian Flautner - Cambridge, GB
Scott Mahlke - Ann Arbor MI, US
Nathan Clark - Ann Arbor MI, US

Assignee:

ARM Limited - Cambridge
University of Michigan - Ann Arbor MI

International Classification:

G06F 9/00

US Classification:

712242

Abstract:

There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising:.

US Patent:

7350055, Mar 25, 2008

Filed:

Jan 31, 2005

Appl. No.:

11/046555

Inventors:

Stuart D. Biles - Cambridge, GB
Krisztian Flautner - Cambridge, GB
Scott Mahlke - Ann Arbor MI, US
Nathan Clark - Ann Arbor MI, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 15/16

US Classification:

712 34, 712218

Abstract:

An accelerator is tightly coupled to the normal execution unit. The operand store, which could be a register file , a stack based operand store or other operand store is shared by the execution unit and the accelerator unit. Operands may also be accessed as immediate values within the instructions themselves. The sequences of individual program instructions corresponding to computational subgraphs remain within a program but can be recognized by the accelerator as suitable for acceleration and when encountered are executed by the accelerator instead of by the normal execution unit. Within such tightly coupled arrangement problems can arise due to a lack of register resources within the system. The present technique provides that at least some intermediate operand values which are generated within the accelerator, but are determined not to be referenced outside of the computational subgraph concerned, are not written to the operand store.

US Patent:

7685404, Mar 23, 2010

Filed:

Jun 5, 2007

Appl. No.:

11/806907

Inventors:

Stuart David Biles - Cambridge, GB
Krisztian Flautner - Cambridge, GB
Scott Mahlke - Ann Arbor MI, US
Nathan Clark - Ann Arbor MI, US

Assignee:

ARM Limited - Cambridge
University of Michigan - Ann Arbor MI

International Classification:

G06F 9/00

US Classification:

712 34, 712242

Abstract:

An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within the program. A memory stores a program formed of separate program instructions. Processing logic executes respective separate program instructions from said program. Accelerator logic, in response to reaching an execution point within the program associated with a subgraph suggestion, executes a sequence of program instructions corresponding to the subgraph suggestion as an accelerated operation instead of executing the sequence of program instructions as respective separate program instructions with the processing logic.

US Patent:

8505002, Aug 6, 2013

Filed:

Sep 27, 2007

Appl. No.:

11/905160

Inventors:

Sami Yehia - Boulogne Billancourt, FR
Krisztian Flautner - Cambridge, GB
Nathan Clark - Ann Arbor MI, US
Amir Hormati - Ann Arbor MI, US
Scott Mahlke - Ann Arbor MI, US

Assignee:

ARM Limited - Cambridge
The Regents of the University of Michigan - Ann Arbor MI

International Classification:

G06F 9/45

US Classification:

717149, 717140, 717150, 717160, 717161

Abstract:

A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.