Naresh C Patel

US Patent:

8015427, Sep 6, 2011

Filed:

Apr 23, 2007

Appl. No.:

11/738841

Inventors:

Steven C. Miller - Sunnyvale CA, US
Naresh Patel - Sunnyvale CA, US

Assignee:

NetApp, Inc. - Sunnyvale CA

International Classification:

G06F 5/06
G06F 1/00
G06F 9/30

US Classification:

713600, 713500, 712205

Abstract:

A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Tto Tby a monitoring module either internal to the processor or operatively interconnected with the processor. Using the measured instruction arrival rates, the monitoring module calculates an optimal instruction arrival rate for each core of the processor. For processors that support continuous frequency changes for cores, each core is then set to an optimal service rate. For processors that only support a discrete set of arrival rates, the optimal rates are mapped to a closest supported rate and the cores are set to the closest supported rate. This procedure is then repeated for each time interval.

US Patent:

8112585, Feb 7, 2012

Filed:

Apr 30, 2009

Appl. No.:

12/433758

Inventors:

Naresh Patel - Sunnyvale CA, US
Jeffrey S. Kimmel - Chapel Hill NC, US
Garth Goodson - Fremont CA, US

Assignee:

NetApp, Inc. - Sunnyvale CA

International Classification:

G06F 12/06

US Classification:

711118, 711 3, 711119

Abstract:

A method implements a cache-policy switching module in a storage system. The storage system includes a cache memory to cache storage data. The cache memory uses a first cache configuration. The cache-policy switching module emulates the caching of the storage data with a plurality of cache configurations. Upon a determination that one of the plurality of cache configurations performs better than the first cache configuration, the cache-policy switching module automatically applies the better performing cache configuration to the cache memory for caching the storage data.

US Patent:

20140033221, Jan 30, 2014

Filed:

Oct 2, 2013

Appl. No.:

14/044583

Inventors:

Naresh M. Patel - Sunnyvale CA, US
Manpreet Singh - Sunnyvale CA, US

Assignee:

NetApp, Inc. - Sunnyvale CA

International Classification:

G06F 9/50
G06F 1/32

US Classification:

718104

Abstract:

Aspects of the present invention concern a method and system for scheduling a request for execution on multiple processors. This scheduler divides processes from the request into a set of domains. Instructions in the same domain are capable of executing the instructions associated with the request in a serial manner on a processor without conflicts. A relative processor utilization for each domain in the set of the domains is based upon a workload corresponding to an execution of the request. If there are processors available then the present invention provisions a subset of available processors to fulfill an aggregate processor utilization. The aggregate processor utilization is created from a combination of the relative processor utilization associated with each domain in the set of domains. If processors are not needed then some processors may be shut down. Shutting down processors in accordance with the schedule saves energy without sacrificing performing.

US Patent:

20150127905, May 7, 2015

Filed:

Nov 5, 2013

Appl. No.:

14/072639

Inventors:

- Sunnyvale CA, US
Ravikanth Dronamraju - Pleasanton CA, US
Mark Smith - Sunnyvale CA, US
Naresh Patel - San Jose CA, US

Assignee:

NETAPP, INC. - Sunnyvale CA

International Classification:

G06F 12/08

US Classification:

711118

Abstract:

A system and method for determining an optimal cache size of a computing system is provided. In some embodiments, the method comprises selecting a portion of an address space of a memory structure of the computing system. A workload of data transactions is monitored to identify a transaction of the workload directed to the portion of the address space. An effect of the transaction on a cache of the computing system is determined, and, based on the determined effect of the transaction, an optimal cache size satisfying a performance target is determined. In one such embodiment the determining of the effect of the transaction on a cache of the computing system includes determining whether the effect would include a cache hit for a first cache size and determining whether the effect would include a cache hit for a second cache size different from the first cache size.

Author:

Naresh M. Patel

ISBN #:

0201544199