Naresh A Patel

Author:

Naresh M. Patel

ISBN #:

0201544199

US Patent:

6372821, Apr 16, 2002

Filed:

Aug 30, 2000

Appl. No.:

09/651824

Inventors:

Naresh D. Patel - Northridge CA
Edward D. Otremba - Orchard Park NY
Rashid H. Siddiqi - South Pasadena CA

Assignee:

IPS Corporation - Gardena CA

International Classification:

C08J 932

US Classification:

523219, 524 99, 524356, 524527, 524567

Abstract:

Novel low VOC solvent-based adhesives are provided, comprising a mixture of low vapor pressure, isomeric dimethyl-2-piperidones (DMPD) blended with (1) a non-solvent diluent, specifically, acetone (a VOC-exempt compound), or with mixtures of acetone and other known ketonic solvents such as methyl ethyl ketone (MEK), diethyl ketone (DEK), methyl propyl ketone (MPK), and methyl iso-butyl ketone (MIBK), cyclohexanone, and (2) thermoplastic PVC or CPVC resins. Omission of the resin provides a novel primer for pipes. The blended mixture yields PVC or CPVC pipe adhesives and primers that: (1) result in low VOC formulas (e. g. , less than 510 g/l for PVC pipe and less than 490 g/l for CPVC pipe); (2) are very economical in the industry; (3) yield strong, quick setting, durable pipe joints that meet the required standards and performance criteria (e. g. , ASTM D-2564 lap shear for PVC); (4) yield stable, low viscosity solutions that, in the case of adhesives, can be readily adjusted with thixotropes (e. g. , Aerosil 200) to give desirable flow characteristics and body, as well as primers for solvent welding PVC and CPVC pipe and components; and (5) can be formulated with minimal (10 wt %) or no cyclic ethers such as THF.

US Patent:

6389017, May 14, 2002

Filed:

Dec 14, 1998

Appl. No.:

09/211696

Inventors:

Naresh Patel - San Jose CA
Karim Harzallah - Mountain View CA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

H04L 1228

US Classification:

370389, 370360

Abstract:

A system and method for scheduling packets between multiple links of an adaptive set utilizes a destination register or a cache line associated with each of the alternate links of the network switch. Each of the cache lines holds the destination of the last packet that used the link. Upon arrival, a packet associatively checks the content of all cache lines. If it hits, then it uses the corresponding link; otherwise, the packet is scheduled according to a round-robin policy or other default policy.

US Patent:

7424577, Sep 9, 2008

Filed:

Aug 26, 2005

Appl. No.:

11/213165

Inventors:

Naveen Bali - Cary NC, US
Naresh Patel - San Jose CA, US
Yasuhiro Endo - San Jose CA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711118, 711133, 711134, 711154

Abstract:

The present invention includes dynamically analyzing look-up requests from a cache look-up algorithm to look-up data block tags corresponding to blocks of data previously inserted into a cache memory, to determine a cache related parameter. After analysis of a specific look-up request, a block of data corresponding to the tag looked up by the look-up request may be accessed from the cache memory or from a mass storage device.

US Patent:

7430639, Sep 30, 2008

Filed:

Aug 26, 2005

Appl. No.:

11/213274

Inventors:

Naveen Bali - Cary NC, US
Naresh Patel - San Jose CA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711133, 711118, 711134, 711154

Abstract:

The present invention includes storing in a main memory data block tags corresponding to blocks of data previously inserted into a buffer cache memory and then evicted from the buffer cache memory or written over in the buffer cache memory. Counters associated with the tags are updated when look-up requests to look up data block tags are received from a cache look-up algorithm.

US Patent:

8015427, Sep 6, 2011

Filed:

Apr 23, 2007

Appl. No.:

11/738841

Inventors:

Steven C. Miller - Sunnyvale CA, US
Naresh Patel - Sunnyvale CA, US

Assignee:

NetApp, Inc. - Sunnyvale CA

International Classification:

G06F 5/06
G06F 1/00
G06F 9/30

US Classification:

713600, 713500, 712205

Abstract:

A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Tto Tby a monitoring module either internal to the processor or operatively interconnected with the processor. Using the measured instruction arrival rates, the monitoring module calculates an optimal instruction arrival rate for each core of the processor. For processors that support continuous frequency changes for cores, each core is then set to an optimal service rate. For processors that only support a discrete set of arrival rates, the optimal rates are mapped to a closest supported rate and the cores are set to the closest supported rate. This procedure is then repeated for each time interval.

US Patent:

8112585, Feb 7, 2012

Filed:

Apr 30, 2009

Appl. No.:

12/433758

Inventors:

Naresh Patel - Sunnyvale CA, US
Jeffrey S. Kimmel - Chapel Hill NC, US
Garth Goodson - Fremont CA, US

Assignee:

NetApp, Inc. - Sunnyvale CA

International Classification:

G06F 12/06

US Classification:

711118, 711 3, 711119

Abstract:

A method implements a cache-policy switching module in a storage system. The storage system includes a cache memory to cache storage data. The cache memory uses a first cache configuration. The cache-policy switching module emulates the caching of the storage data with a plurality of cache configurations. Upon a determination that one of the plurality of cache configurations performs better than the first cache configuration, the cache-policy switching module automatically applies the better performing cache configuration to the cache memory for caching the storage data.

US Patent:

8176251, May 8, 2012

Filed:

Aug 5, 2008

Appl. No.:

12/186507

Inventors:

Naveen Bali - Cary NC, US
Naresh Patel - San Jose CA, US
Yasuhiro Endo - San Jose CA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711118, 711133, 711134, 711154

Abstract:

The present invention includes dynamically analyzing look-up requests from a cache look-up algorithm to look-up data block tags corresponding to blocks of data previously inserted into a cache memory, to determine a cache related parameter. After analysis of a specific look-up request, a block of data corresponding to the tag looked up by the look-up request may be accessed from the cache memory or from a mass storage device.

US Patent:

8255630, Aug 28, 2012

Filed:

Aug 13, 2008

Appl. No.:

12/191272

Inventors:

Naveen Bali - Cary NC, US
Naresh Patel - San Jose CA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711133, 711118, 711122, 711144, 711154

Abstract:

The present invention includes storing in a main memory data block tags corresponding to blocks of data previously inserted into a buffer cache memory and then evicted from the buffer cache memory or written over in the buffer cache memory. Counters associated with the tags are updated when look-up requests to look up data block tags are received from a cache look-up algorithm.