Narasimhan S Vasudevan from 11745 Semillon Blvd, San Diego, CA 92131, age 52

Resumes

Exective Director

view source

Location:

San Diego, CA

Industry:

Automotive

Work:

Qualcomm - Greater San Diego Area since Jun 2011
Staff Engineer
Xilinx Apr 1998 - Jun 2011
Staff IC Design Engineer

Education:

Duke University
MS, Electrical Engineering Duke University
PhD, Electrical Engineering Indian Institute of Technology, Madras
B.Tech, Electronics & Communication Engineering

Skills:

Phy
Design
Analog
Digital Circuit Design

Narasimhan Vasudevan

view source

Us Patents

Supply Regulator For Memory Cells With Suspend Mode Capability For Low Power Applications
view source
US Patent:

7265605, Sep 4, 2007
Filed:

Oct 18, 2005
Appl. No.:

11/252504
Inventors:

Narasimhan Vasudevan - Los Angeles CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G05F 1/10
US Classification:

327534
Abstract:

An integrated circuit (IC) device includes a first voltage supply for powering first circuitry within the device, a second voltage supply for powering second circuitry within the device, a suspend circuit having an output to generate a power-down signal, and a voltage regulator circuit coupled to a power node. The voltage regulator circuit includes a first transistor coupled between the first voltage supply and the power node and having a gate responsive to a regulation signal, a second transistor coupled between the second voltage supply and the power node and having a gate responsive to the power-down signal, and a well bias circuit having an input coupled to receive the power-down signal, a first output coupled to a well region of the first transistor, and a second output coupled to a well region of the second transistor.

Bandgap System With Tunable Temperature Coefficient Of The Output Voltage
view source
US Patent:

7307468, Dec 11, 2007
Filed:

Jan 31, 2006
Appl. No.:

11/343555
Inventors:

Narasimhan Vasudevan - Los Angeles CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G05F 1/10
G05F 3/02
US Classification:

327539
Abstract:

A voltage supply circuit for generating a composite bandgap reference voltage includes a single bandgap reference voltage circuit and a select circuit. The bandgap reference circuit has a first output to generate a first bandgap voltage having a first temperature coefficient and has a second output to generate a second bandgap voltage having a second temperature coefficient that is different from the first temperature coefficient. The select circuit has a first input to receive the first bandgap voltage, a second input to receive the second bandgap voltage, and an output to selectively provide either the first bandgap voltage or the second bandgap voltage as the composite bandgap reference voltage.

Highly Reliable And Zero Static Current Start-Up Circuits
view source
US Patent:

7321256, Jan 22, 2008
Filed:

Oct 18, 2005
Appl. No.:

11/252679
Inventors:

Narasimhan Vasudevan - Los Angeles CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G05F 3/04
US Classification:

327539, 323313
Abstract:

A bandgap reference voltage circuit includes a bandgap circuit, a start-up circuit, and a recovery circuit. Upon device power-on, the start-up circuit provides a start-up current to initialize the bandgap circuit to a valid state, during which the bandgap circuit generates a substantially constant bandgap reference voltage. Once the bandgap circuit is in the valid state, the start-up circuit turns itself off. If the bandgap reference voltage falls to a level that causes the bandgap circuit to enter an invalid state, the recovery circuit turns on and provides a recovery current to the bandgap circuit that returns the bandgap circuit to the valid state, after which the recovery circuit turns itself off.

Power-On Reset Circuit For A Voltage Regulator Having Multiple Power Supply Voltages
view source
US Patent:

7667489, Feb 23, 2010
Filed:

Oct 26, 2007
Appl. No.:

11/977831
Inventors:

Narasimhan Vasudevan - Los Angeles CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

H03K 19/00
H03K 19/02
H03K 19/096
US Classification:

326 57, 326 56, 326 58, 326 93, 326 94, 326 95, 326 96, 326 97, 326 98
Abstract:

A voltage regulator and method of voltage regulation for a power-on reset condition are described. Voltage regulation control signals responsive to the power-on reset condition are obtained. The control signals are generated with a first voltage to be associated with a second voltage to provide a first power-on-reset signal and a second power-on-reset signal which are opposite in state to one another. A portion of driver logic is tri-stated responsive to the control signals, and the second power-on-reset signal to at least impede supply to supply current leakage. Voltage is pulled up on a first output port and a second output port of the driver logic responsive to the first power-on-reset signal. A portion of a semiconductor substrate is electrically coupled to a higher one of a first voltage and a second voltage responsive to the pulling up to at least further impede the supply to supply current leakage.

Enhanced Voltage Regulation With Power Supply Disable Capability For Low-Power Operation
view source
US Patent:

7701245, Apr 20, 2010
Filed:

Oct 26, 2007
Appl. No.:

11/977863
Inventors:

Narasimhan Vasudevan - Los Angeles CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

H03K 17/16
H03K 19/003
US Classification:

326 33, 327537, 327541, 327544
Abstract:

A method and apparatus is provided that facilitates low-power consumption during a suspend mode of operation of an integrated circuit (IC), while substantially eliminating current paths within the IC that may be created should any of the power supplies be deactivated during the suspend mode. Deactivation of one or more power supplies during a normal mode of operation is also facilitated, whereby current paths created by the deactivated power supplies are also eliminated. Voltage bias circuitry is added to certain voltage regulators within the IC, so as to maintain those voltage regulators inactive due to a drop in voltage magnitude that is sensed when one or more power supplies are disabled. In addition, a well bias circuit is employed to maintain the substrate bias potential of certain devices within the voltage regulators and associated amplifiers to a fixed potential depending upon the operational mode of the IC.

Voltage Sensing In A Supply Regulator For A Suspend Mode
view source
US Patent:

7733075, Jun 8, 2010
Filed:

Oct 26, 2007
Appl. No.:

11/978010
Inventors:

Narasimhan Vasudevan - Los Angeles CA, US
Assignee:

XILINX, Inc. - San Jose CA
International Classification:

G05F 3/16
US Classification:

323314
Abstract:

A voltage regulator for supplying power to volatile memory cells during a suspend mode of an integrated circuit is described. The integrated circuit in an awake mode generates a regulated voltage at an output node using a first supply voltage and in the suspend mode generates the regulated voltage at the output node using a second supply voltage, at less voltage than the first supply voltage. The second supply voltage is electrically decoupled from the output node for transitioning from the suspend mode to the awake mode, and the first supply voltage is electrically decoupled from the output node for transitioning from the awake mode to the suspend mode.

Method And Apparatus For Saving And Restoring The State Of A Power-Gated Memory Device
view source
US Patent:

7859936, Dec 28, 2010
Filed:

Jan 26, 2009
Appl. No.:

12/359996
Inventors:

Narasimhan Vasudevan - San Jose CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G11C 5/14
US Classification:

365227, 36518917, 36518908, 365154, 36518905, 36523008
Abstract:

A method and apparatus involving a circuit is disclosed. The circuit has separate first and second portions, where the first portion includes a first memory device such as a flip-flop, and the second portion includes a second memory device such as a latch. The first portion is selectively operated in first and second operational modes, the first portion consuming less power in the second operational mode than in the first operational mode. During the first operational mode a logical value is maintained in the flip-flop and can vary dynamically. During the second operational mode, the state that the logical value had at a point in time just before the first portion entered the second operational mode is maintained in the latch. Then, after the first portion switches from the second operational mode back to the first operational mode, the state of the logical value in the latch is restored to the flip-flop.

Stable Vco Operation In Absence Of Clock Signal
view source
US Patent:

8120430, Feb 21, 2012
Filed:

Jan 15, 2009
Appl. No.:

12/354614
Inventors:

Narasimhan Vasudevan - Los Angeles CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

H03L 7/00
US Classification:

331 16, 331 17, 331 44, 331182, 331183, 331186
Abstract:

A semiconductor device having a phase-locked loop (“PLL”) () drives a VCO () of the PLL circuit with a first control voltage (V) produced by a loop filter () when a first clock signal (clk_ref) is present. The VCO produces an output frequency while the PLL circuit is operating off the first clock signal. When the first clock signal is lost (ref_lost), a control voltage maintenance circuit () produces a second control voltage maintaining the VCO output frequency. In one device, the control voltage maintenance circuit includes a phase-frequency detector () that can operate off of either the clock reference signal or a master clock signal. In an alternative device, the control voltage maintenance circuit includes a voltage generator () that produces a generated voltage that drives the loop filter when lock is lost.