Nafea Bshara

US Patent:

8089963, Jan 3, 2012

Filed:

Sep 13, 2010

Appl. No.:

12/881123

Inventors:

David Melman - Hakerem, IL
Nir Arad - Nesher, IL
Nafea Bshara - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton
Marvell Israel (M.I.S.L) Ltd. - Yokneam

International Classification:

H04L 12/28

US Classification:

370389, 370474, 370473, 709232, 709251

Abstract:

A network device includes at least one source physical port coupled to a network, and a plurality of egress ports. A logical port assignment mechanism assigns source logical port information to a data packet received via one of the at least one physical port. The source logical port information is based on characteristics of the data packet, and the source logical port information corresponds to a logical entity that is different from any source physical port. A forwarding engine determines one or more egress ports for forwarding the data packet based on at least the assigned source logical port.

US Patent:

8514651, Aug 20, 2013

Filed:

Nov 22, 2011

Appl. No.:

13/302837

Inventors:

Gil Levy - Hod Hasharon, IL
Nafea Bshara - San Jose CA, US
Yaron Zimerman - Kiryat Ono, IL
Carmi Arad - Nofit, IL

Assignee:

Marvell World Trade Ltd. - St. Michael
Marvell Israel (M.I.S.L) Ltd. - Yokneam

International Classification:

G11C 8/00

US Classification:

36523003, 36518509

Abstract:

In a memory device having a set of memory banks to store content data, at least two requests to perform respective memory operations in a first memory bank are received during a single clock cycle. One or more of the at least two requests is blocked from accessing the first memory bank, and in response: redundancy data associated with the first memory bank and different from content data stored therein is accessed, and, without accessing the first memory bank, at least a portion of the content data stored in the first memory bank is reconstructed based on the associated redundancy data. A first memory operation is performed using the content data stored in the first memory bank, and a second memory operation is performed using content data reconstructed i) without accessing the first memory bank and ii) based on the associated redundancy data.

US Patent:

20080225853, Sep 18, 2008

Filed:

Feb 13, 2008

Appl. No.:

12/030822

Inventors:

David MELMAN - D.N. Bikat Beit Hakerem, IL
Nir ARAD - Nesher, IL
Nafea BShara - San Jose CA, US

International Classification:

H04L 12/56

US Classification:

370392

Abstract:

A system and method of extending a standard bridge to enable execution of logical bridging functionality are disclosed. In some implementations, a logical bridge may assign source logical port information to a data packet based on characteristics of the data packet, employ the source logical port information to learn the source address and to forward the data packet to a logical egress port, and map the logical egress port to a physical egress port at which the data packet is to be egressed. A tunnel interface may optionally be applied to a data packet upon egress.

US Patent:

20120106553, May 3, 2012

Filed:

Dec 29, 2011

Appl. No.:

13/340393

Inventors:

DAVID MELMAN - Hakerem, IL
Nir Arad - Nesher, IL
Nafea Bshara - San Jose CA, US

International Classification:

H04L 12/56

US Classification:

370392

Abstract:

A network device includes at least one source physical port configured to be coupled to a network, a plurality of egress ports, and a packet processor. The packet processor includes a processing stage configured to implement a logical port assignment mechanism to assign source logical port information to a data packet received via one of the at least one source physical port, wherein the source logical port information is based on characteristics of the data packet, wherein the source logical port information corresponds to a logical entity that is different from any source physical port, and a forwarding engine to determine one or more egress ports for forwarding the data packet based on at least the assigned source logical port information.

US Patent:

20220278941, Sep 1, 2022

Filed:

May 13, 2022

Appl. No.:

17/663398

Inventors:

- Seattle WA, US
Brian William Barrett - Seattle WA, US
Nafea Bshara - San Jose CA, US
Georgy Machulsky - San Jose CA, US

International Classification:

H04L 47/62
H04L 45/74
H04L 45/24
G06F 15/173
H04L 1/18
H04L 69/22
H04L 49/90
H04L 69/326
H04L 47/34
H04L 69/324

Abstract:

Provided are systems and methods for reliable, out-of-order transmission of packets. In some implementations, provided is an apparatus configured to communicate with a network and a host device. The apparatus may receive out-of-order packets from a remote device. The apparatus may transmit selective-acknowledgements to the remote device such that remote device can retransmit certain packets. The out-of-order packets can be provided to software for re-ordering.

US Patent:

20230018032, Jan 19, 2023

Filed:

Sep 23, 2022

Appl. No.:

17/952144

Inventors:

- Seattle WA, US
Christopher Joseph Pettey - Woodinville WA, US
Asif Khan - Cedar Park TX, US
Robert Michael Johnson - Austin TX, US
Mark Bradley Davis - Austin TX, US
Erez Izenberg - Tel Aviv, IL
Nafea Bshara - San Jose CA, US
Kypros Constantinides - Seattle WA, US

International Classification:

G06F 13/40
G06F 9/445
G06F 13/42
G06F 15/78

Abstract:

The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

US Patent:

20230004521, Jan 5, 2023

Filed:

Sep 1, 2022

Appl. No.:

17/901720

Inventors:

- Seattle WA, US
Leah Shalev - Zichron Yaakov, IL
Nafea Bshara - San Jose CA, US
Guy Nakibly - Kedumim, IL
Georgy Machulsky - San Jose CA, US

Assignee:

Amazon Technologies, Inc. - Seattle WA

International Classification:

G06F 15/167
H04L 69/22
G06F 16/22

Abstract:

Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

US Patent:

20230006934, Jan 5, 2023

Filed:

Sep 12, 2022

Appl. No.:

17/931425

Inventors:

- Seattle WA, US
Nafea Bshara - San Jose CA, US
Georgy Machulsky - San Jose CA, US
Brian William Barrett - Seattle WA, US

International Classification:

H04L 47/125
G06F 9/448
H04L 69/10
G06F 9/50
H04L 61/5007
H04L 65/40
H04L 43/0823
H04L 43/0852
H04L 45/24
H04L 45/00
H04L 45/74
H04L 49/25
H04L 69/16
H04L 69/22

Abstract:

Disclosed herein is a method including receiving, from a user application, data to be transmitted from a source address to a destination address using a single connection through a network; and splitting the data into a plurality of packets according to a communication protocol. For each packet of the plurality of packets, a respective flowlet for the packet to be transmitted in is determined from a plurality of flowlets. Assignment of the flowlets to the packets can be dynamically adjusted based on utilization of the flowlets.