Murali N Iyer

US Patent:

8516164, Aug 20, 2013

Filed:

May 24, 2011

Appl. No.:

13/114390

Inventors:

Brian E. Bakke - Rochester MN, US
Brian L. Bowles - Rochester MN, US
Michael J. Carnevale - Rochester MN, US
Adrian C. Gerhard - Rochester MN, US
Murali N. Iyer - Rochester MN, US
Daniel F. Moertl - Rochester MN, US
Mark J. Moran - Minneapolis MN, US
Gowrisankar Radhakrishnan - Rochester MN, US
Rick A. Weckwerth - Oronoco MN, US
Donald J. Ziebarth - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/28

US Classification:

710 22, 710 24

Abstract:

A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.

US Patent:

8544029, Sep 24, 2013

Filed:

May 24, 2011

Appl. No.:

13/114107

Inventors:

Brian E. Bakke - Rochester MN, US
Brian L. Bowles - Rochester MN, US
Michael J. Carnevale - Rochester MN, US
Adrian C. Gerhard - Rochester MN, US
Murali N. Iyer - Rochester MN, US
Daniel F. Moertl - Rochester MN, US
Mark J. Moran - Minneapolis MN, US
Gowrisankar Radhakrishnan - Rochester MN, US
Rick A. Weckwerth - Oronoco MN, US
Donald J. Ziebarth - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44
G06F 13/28

US Classification:

719318, 710 22

Abstract:

A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.

US Patent:

20090327562, Dec 31, 2009

Filed:

Jun 25, 2008

Appl. No.:

12/145761

Inventors:

Mark David Bellows - Rochester MN, US
Brian Patrick Burgess - Rochester MN, US
John Dennis Folkerts - Rochester MN, US
Roger John Gravrok - Eau Claire WI, US
Brian Gerard Holthaus - Oronoco MN, US
Murali N. Iyer - Rochester MN, US
Christopher James Martin - Cincinnati OH, US
Timothy Gerald Robeck - Rochester MN, US
Dennis J. Spathis - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 13/00

US Classification:

710305

Abstract:

A method and apparatus are provided for implementing bus interface calibration to improve bus interface initialization time in a system. Bus interface calibration is performed and average calibration values are saved. At bus interface initialization time, checking for saved calibration values is performed. The saved calibration values are used and tested. When the saved calibration values pass the test, then the saved calibration values are used for system operation without performing any training steps.

US Patent:

20120278528, Nov 1, 2012

Filed:

Apr 28, 2011

Appl. No.:

13/096222

Inventors:

Robert E. Galbraith - Rochester MN, US
Murali N. Iyer - Rochester MN, US
Timothy J. Larson - LaCrosse WI, US
Steven P. Norgaard - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/02

US Classification:

711103, 711E12008

Abstract:

A method and controller for implementing enhanced flash backed dynamic random access memory (DRAM) management, and a design structure on which the subject controller circuit resides are provided. An input/output adapter (IOA) includes at least one super capacitor, a data store (DS) dynamic random access memory (DRAM), a flash memory, a non-volatile random access memory (NVRAM), and a flash backed DRAM controller. Responsive to an adapter reset, Data Store DRAM testing including restoring a DRAM image from Flash to DRAM and testing of DRAM is performed. Mirroring of RAID configuration data and RAID parity update footprints between the NVRAM and DRAM is performed. Save of DRAM contents to the flash memory is controllably enabled when super capacitors have been sufficiently recharged and the flash memory erased.

US Patent:

20120303855, Nov 29, 2012

Filed:

May 24, 2011

Appl. No.:

13/114124

Inventors:

Brian E. Bakke - Rochester MN, US
Brian L. Bowles - Rochester MN, US
Michael J. Carnevale - Rochester MN, US
Adrian C. Gerhard - Rochester MN, US
Murali N. Iyer - Rochester MN, US
Daniel F. Moertl - Rochester MN, US
Mark J. Moran - Minneapolis MN, US
Gowrisankar Radhakrishnan - Rochester MN, US
Rick A. Weckwerth - Oronoco MN, US
Donald J. Ziebarth - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 13/28

US Classification:

710308

Abstract:

A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.

US Patent:

20120303859, Nov 29, 2012

Filed:

May 24, 2011

Appl. No.:

13/114268

Inventors:

Brian E. Bakke - Rochester MN, US
Brian L. Bowles - Rochester MN, US
Michael J. Carnevale - Rochester MN, US
Robert E. Galbraith - Rochester MN, US
Adrian C. Gerhard - Rochester MN, US
Murali N. Iyer - Rochester MN, US
Daniel F. Moertl - Rochester MN, US
Mark J. Moran - Minneapolis MN, US
Gowrisankar Radhakrishnan - Rochester MN, US
Rick A. Weckwerth - Oronoco MN, US
Donald J. Ziebarth - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/00

US Classification:

711102, 711E12001

Abstract:

A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.

US Patent:

20120303883, Nov 29, 2012

Filed:

May 24, 2011

Appl. No.:

13/114185

Inventors:

Brian E. Bakke - Rochester MN, US
Brian L. Bowles - Rochester MN, US
Michael J. Carnevale - Rochester MN, US
Adrian C. Gerhard - Rochester MN, US
Murali N. Iyer - Rochester MN, US
Daniel F. Moertl - Rochester MN, US
Mark J. Moran - Minneapolis MN, US
Gowrisankar Radhakrishnan - Rochester MN, US
Rick A. Weckwerth - Oronoco MN, US
Donald J. Ziebarth - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/08
G06F 12/00

US Classification:

711105, 711118, 711E12001, 711E12041

Abstract:

A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.

US Patent:

20120303886, Nov 29, 2012

Filed:

May 24, 2011

Appl. No.:

13/114291

Inventors:

Brian E. Bakke - Rochester MN, US
Brian L. Bowles - Rochester MN, US
Michael J. Carnevale - Rochester MN, US
Robert E. Galbraith - Rochester MN, US
Adrian C. Gerhard - Rochester MN, US
Murali N. Iyer - Rochester MN, US
Daniel F. Moertl - Rochester MN, US
Mark J. Moran - Minneapolis MN, US
Gowrisankar Radhakrishnan - Rochester MN, US
Rick A. Weckwerth - Oronoco MN, US
Donald J. Ziebarth - Rochester MN, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 12/00
G06F 12/08

US Classification:

711113, 711114, 711154, 711E12001, 711E12019

Abstract:

A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.