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Morton B Panish

age ~95

from Freeport, ME

Also known as:
  • Mort Panish
  • Morton B Pamish
Phone and address:
52 Baldwin Rd, Freeport, ME 04032
207 865-3969

Morton Panish Phones & Addresses

  • 52 Baldwin Rd, Freeport, ME 04032 • 207 865-3969
  • 278 Foreside Rd, Falmouth, ME 04105 • 207 899-0926
  • Portland, ME
  • 9 Persimmon Way, Springfield, NJ 07081 • 908 277-3390
  • 9 Persimmon Way, Springfield, NJ 07081 • 973 865-2572

Work

  • Position:
    Production Occupations

Education

  • Degree:
    Associate degree or higher

Resumes

Morton Panish Photo 1

Retired

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Location:
Portland, ME
Industry:
Arts And Crafts
Work:
Self - Employed (Special Projects) - Freeport, Maine since Mar 1992
Retired

AT&T Bell Labs Jun 1964 - Mar 1992
Distinguished Member of Technical Staff
Education:
Michigan State University 1950 - 1954
Ph.D., Physical Chemistry
Morton Panish Photo 2

Morton Panish

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Morton Panish Photo 3

Morton Panish

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Location:
United States

Us Patents

  • Method Of Growing Iii-V Semiconductor Layers With High Effective Hole Concentration

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  • US Patent:
    49391020, Jul 3, 1990
  • Filed:
    Jan 17, 1989
  • Appl. No.:
    7/297716
  • Inventors:
    Robert A. Hamm - Staten Island NY
    Roger J. Malik - Summit NJ
    Morton B. Panish - Springfield NJ
    John F. Walker - Westfield NJ
  • Assignee:
    American Telephone and Telegraph Company - New York NY
  • International Classification:
    H01L 21203
  • US Classification:
    437107
  • Abstract:
    36 We have discovered the III-V semiconductor layers with previously unattainably high effective hole concentrations can be produced by molecular growth processes (e. g. MBE) if an amphoteric dopant such as Be is used and if, during the growth of the highly doped III-V layer, the substrate is maintained at a temperature T. sub. g that is substantially lower than customarily used. For instance, a InGaAs layer with effective hole concentration 1. times. 10. sup. 20 cm. sup. -3 was grown at T. sub. g =450. degree. C. , and a GaAs layer with effective hole concentration of 1. times. 10. sup. 20 cm. sup. -3 was grown at T. sub. g of 475. degree. C. The heavily doped III-V layers can be of device grade and can usefully be part of electronic devices such as high speed bipolar transistors.
  • Mbe Growth: Gettering Contaminants And Fabricating Heterostructure Junction Lasers

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  • US Patent:
    39740021, Aug 10, 1976
  • Filed:
    Jun 10, 1974
  • Appl. No.:
    5/477975
  • Inventors:
    Horace Craig Casey - Summit NJ
    Alfred Yi Cho - New Providence NJ
    Morton B. Panish - Springfield NJ
  • Assignee:
    Bell Telephone Laboratories, Incorporated - Murray Hill NJ
  • International Classification:
    H01L 736
  • US Classification:
    148175
  • Abstract:
    In the fabrication of double heterostructure GaAsAlGaAs junction lasers by molecular beam epitaxy, it has been found that suitably annealing the entire heterostructure increases the external quantum efficiency of the laser and reduces the room temperature threshold for lasing. Also described is a technique using relatively uncollimated beams to deposit continuously on the interior walls of the vacuum chamber fresh layers which getter deleterious contaminants. In addition, pyrolytic boron nitride, rather than graphite, effusion cells are utilized in order to reduce the amount of CO formation in the system.
  • Device Fabrication

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  • US Patent:
    51067641, Apr 21, 1992
  • Filed:
    Nov 30, 1989
  • Appl. No.:
    7/444579
  • Inventors:
    Lloyd R. Harriott - Somerville NJ
    Morton B. Panish - Springfield NJ
    Henryk Temkin - Berkeley Heights NJ
    Yuh-Lin Wang - North Plainfield NJ
  • Assignee:
    AT&T Bell Laboratories - Murray Hill NJ
  • International Classification:
    H01L 21302
  • US Classification:
    437 18
  • Abstract:
    Fine featured devices are produced by a series of fabrication steps including exposing selective surface regions to irradiation, e. g. to an ion beam, generally to result in removal of masking material within irradiated regions. In most instances, subsequent etching is under conditions such that bared material is preferentially removed. Etch-removal and irradiation are such that overgrown material is of device quality at least in etched regions. The inventive process is of particular value in the fabrication of integrated circuits, e. g. circuits performing electronic and/or optical functions. The inventive process is expediently used in the fabrication of structures having minimum feature size of 1 micrometer and smaller. Patterning is dependent upon masking material of a maximum thickness of 100. ANG.
  • Molecular Beam Deposition Technique Using Gaseous Sources Of Group V Elements

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  • US Patent:
    43303609, May 18, 1982
  • Filed:
    Jul 21, 1980
  • Appl. No.:
    6/170548
  • Inventors:
    Glenn D. Kubiak - Palo Alto CA
    Morton B. Panish - Springfield NJ
  • Assignee:
    Bell Telephone Laboratories, Incorporated - Murray Hill NJ
  • International Classification:
    C30B 2306
  • US Classification:
    156610
  • Abstract:
    The invention is a method and apparatus for growing group III-V semiconductor layers by molecular beam deposition in which a gaseous source is used to form a molecular beam comprising M. sub. 2 or M. sub. 4 molecules, where M is a group V element. Arsine and phosphine may be decomposed in a high temperature leak-source to provide As. sub. 2 and P. sub. 2 molecular beams for molecular beam epitaxy of group III-V semiconductors such as GaAs and InP.
  • Light Emitting Diodes Which Emit In The Infrared

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  • US Patent:
    41841719, Jan 15, 1980
  • Filed:
    Jul 5, 1978
  • Appl. No.:
    5/921983
  • Inventors:
    Morton B. Panish - Springfield NJ
  • Assignee:
    Bell Telephone Laboratories, Incorporated - Murray Hill NJ
  • International Classification:
    H01S 3319
    H01L 3300
  • US Classification:
    357 18
  • Abstract:
    A semiconductor double heterostructure (DH) laser or spontaneous emitting diode is described which emits radiation in the infrared region of the spectrum from about 3. 5 to 5. 5 micrometers. The DH structure comprises a Group III-V lattice-matched system, in particular, Al. sub. y Ga. sub. 1-y Sb--InAs. sub. x Sb. sub. 1-x where 0. ltoreq. y. gtoreq. 1 and 0. 82. ltoreq. times. ltoreq. 91, approximately.
  • Stress Reduction In Algaas-Algaasp Multilayer Structures

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  • US Patent:
    39582639, May 18, 1976
  • Filed:
    Apr 25, 1974
  • Appl. No.:
    5/463871
  • Inventors:
    Morton B. Panish - Springfield NJ
    George Arthur Rozgonyi - Chatham NJ
  • Assignee:
    Bell Telephone Laboratories, Incorporated - Murray Hill NJ
  • International Classification:
    H01S 3319
    H01L 29161
    H01L 29205
  • US Classification:
    357 18
  • Abstract:
    The average stress between contiguous layers of Al. sub. x Ga. sub. 1. sub. -x As and Al. sub. y Ga. sub. 1. sub. -y As (y > x) is reduced by the addition of phosphorus during the growth of the latter layer to produce the quaternary Al. sub. y Ga. sub. 1. sub. -y As. sub. 1. sub. -z P. sub. z instead of the ternary Al. sub. y Ga. sub. 1. sub. -y As. In order to reduce the average stress to less than about 2. times. 10. sup. 8 dynes/cm. sup. 2 the amount of phosphorus added should satisfy the condition: ##EQU1## Also described is a double heterostructure junction laser comprising a GaAs or AlGaAs active layer sandwiched between layers of AlGaAsP.
  • Heterostructure Bipolar Transistor

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  • US Patent:
    52065243, Apr 27, 1993
  • Filed:
    Jun 20, 1991
  • Appl. No.:
    7/721913
  • Inventors:
    Anthony F. J. Levi - Summit NJ
    Richard N. Nottenburg - New York NY
    Morton Panish - Springfield NJ
  • Assignee:
    AT&T Bell Laboratories - Murray Hill NJ
  • International Classification:
    H01L 2972
  • US Classification:
    257 29
  • Abstract:
    Improved heterojunction bipolar transistor (HBT) are disclosed. Inventive devices can attain high cut-off frequency (f. sub. T), exemplarily 80 GHz or higher, and high DC current gain (. beta. ), exemplarily 25 or higher. The devices exhibit lateral scaling, permitting reduction in emitter stripe width without unacceptable decrease in. beta. Exemplarily the stripe width is 1. mu. m or less. The inventive HBTs are hot electron devices, with the hot electrons in the base region being spatially confined such that relatively few electrons reach the surface of the extrinsic base region. The relatively low bulk and surface recombination rate in the base of inventive HBTs is an important aspect of the invention and makes possible devices having relatively high. beta. and low power consumption. Appropriate choice of base material, namely, a semiconductor material having relatively low intrinsic surface recombination velocity, can result in further reduction of surface recombination, as can, for instance, the use of an appropriate non-alloyed metal base contact.
  • Patterning Method In The Manufacture Of Miniaturized Devices

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  • US Patent:
    48973610, Jan 30, 1990
  • Filed:
    Dec 14, 1987
  • Appl. No.:
    7/132757
  • Inventors:
    Lloyd R. Harriott - Hillsborough Township, Somerset County NJ
    Morton B. Panish - Springfield NJ
    Henryk Temkin - Berkeley Heights NJ
  • Assignee:
    American Telephone & Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ
  • International Classification:
    H01L 21265
    H01L 2120
  • US Classification:
    437 24
  • Abstract:
    When high-vacuum methods are used in the manufacture of miniaturized devices such as, e. g. , semiconductor integrated-circuit devices, device layers on a substrate are preferably patterned without breaking of the vacuum. Preferred patterning involves deposition of a semiconductor mask layer, generation of the pattern in the mask layer by ion deflected-beam writing, and transfer of the pattern by dry etching. When the mask layer is an epitaxial layer, further epitaxial layer deposition after patterning may proceed without removal of remaining mask layer material.

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Morton Panish Photo 4

Morton Panish

Lived:
Freeport, Maine
Brooklyn, N.Y.
Colo., Mich, Tenn, Mass, NJ, Maine
Work:
None - Retired Scientist, Photographer, loafer
Oak Ridge Nat. Lab, Avco Corp., AT&T Bell Labs
Education:
None, Erasmus Hall High School, Brooklyn College, Denver Univ., Mich State Univ.

Youtube

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PJ Morton - Gumbo Unplugged (Live)

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PJ Morton live at Paste Studio NYC

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PJ Morton - Be Like Water (Acoustic Session)

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MORTON - Escapist (official audio)

MORTON "Horror of Daniel Wagner" Track#8: Escapist Full album stream: ...

  • Duration:
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Maroon 5 ft PJ Morton - Is Anybody Out There?...

Maroon 5 produced 'Is Anybody Out There' within 24 hours. The making o...

  • Duration:
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AT&T Archives: Inventing the Laser at Bell Labs

1971: Izuo Hayashi and Morton Panish design the first semiconductor la...

  • Duration:
    11m 51s

MORTON - No Fear of Flight (official audio)

MORTON "Horror of Daniel Wagner" Track#7: No Fear of Flight Full album...

  • Duration:
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