Moinul I Syed

US Patent:

6954869, Oct 11, 2005

Filed:

Sep 26, 2002

Appl. No.:

10/255477

Inventors:

Moinul I. Syed - Austin TX, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F001/12
G06F001/06
G06F001/04

US Classification:

713400, 713500, 713600

Abstract:

Methods and apparatus are provided for clock domain conversion in digital processing systems. The methods include operating a first circuit in a fast clock domain with a fast clock and operating a second circuit in a slow clock domain with a slow clock. To transfer signals from the fast clock domain to the slow clock domain, a first synchronization signal is asserted during each fast clock cycle in which a slow clock edge occurs. A fast signal is transferred from the fast clock domain to the slow clock domain on a fast clock edge when the first synchronization signal is asserted. To transfer signals from the slow clock domain to the fast clock domain, a second synchronization signal is asserted during each fast clock cycle that immediately follows a slow clock edge. A slow signal is transferred from the slow clock domain to the fast clock domain on a fast clock edge when the second synchronization signal is asserted.

US Patent:

6988167, Jan 17, 2006

Filed:

Feb 8, 2001

Appl. No.:

09/779209

Inventors:

Michael S. Allen - Austin TX, US
Moinul I. Syed - Austin TX, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 12/00

US Classification:

711128, 710 26, 710 27, 710 28

Abstract:

In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data available to the processor application before the application references the data, thereby potentially providing a 100% cache hit ratio since the correct data is pre-loaded into the cache. In addition, if a copy-back cache is employed, the cache memory system can also be configured such that processed data can be dynamically unloaded from the cache to the main memory in parallel with accesses to the cache made by the core processor. The pre-loading and/or post unloading of data may be accomplished, for example, by using a DMA controller to burst data into and out of the cache in parallel with accesses to the cache by the core processor. This DMA control function may be integrated into the existing cache control logic so as to reduce the complexity of the cache hardware (e. g. , as compared to a multi-port cache), and to alleviate the difficulty associated with addressing the non-contiguous internal address map of the cache.

US Patent:

7702862, Apr 20, 2010

Filed:

Feb 8, 2007

Appl. No.:

11/704143

Inventors:

Moinul I. Syed - Austin TX, US
Richard A. Gentile - Natick MA, US
Gregory T. Koker - Newton MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 12/00
G06F 11/34

US Classification:

711154, 714E11201, 714E11205

Abstract:

A processing system includes a processing circuit having one or more buses, a memory interface unit to control access by the processing circuit to a memory, and a metrics module. The metrics module includes one or more metrics registers and a metrics controller to monitor one or more operations selected from memory interface unit operations and bus operations, and to store metrics information corresponding to the monitored operations in the metrics registers. The monitored operations can include memory access operations, arbitration operations, bus operations, and the like. The metrics information can be analyzed to provide a basis for improving performance of a program that is executed on the processing system.

US Patent:

20020108021, Aug 8, 2002

Filed:

Feb 8, 2001

Appl. No.:

09/779803

Inventors:

Moinul Syed - Austin TX, US
Michael Allen - Austin TX, US

International Classification:

G06F013/00

US Classification:

711/128000

Abstract:

After one way of an associative cache is disabled from the perspective of a core processor, a DMA data transfer operation may be commenced to pre-load data into the disabled way from a main memory or to unload data from the disabled way into the main memory. By using a separate decoder for each way of the cache, a few additional multiplexers, and additional control circuitry, different ways of a cache may be accessed concurrently by the core processor and the DMA controller. Therefore, while a DMA transfer operation takes place with respect to the disabled way of the cache, the other ways of the cache remain accessible by the core processor. By properly pre-loading and unloading data from selected ways of the cache in this manner, the cache hit ratio by the core processor can approach 100%.

US Patent:

20040064662, Apr 1, 2004

Filed:

Sep 26, 2002

Appl. No.:

10/255975

Inventors:

Moinul Syed - Austin TX, US
Michael Allen - Austin TX, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F012/00

US Classification:

711/169000, 711/158000

Abstract:

A bus interface unit is provided for a digital signal processor including a core processor, a memory and two or more system buses for transfer of data to and from system components. The bus interface unit includes a first bus controller for receiving processor transfer requests from the core processor on two or more processor buses and for directing the processor transfer requests to the memory on a first memory bus. The bus interface further includes a second bus controller for receiving system transfer requests from the system components on the two or more system buses and for directing the system transfer requests to the memory on a second memory bus. The bus controllers may have pipelined architectures and may be configured to service transfer requests independently.

US Patent:

6446181, Sep 3, 2002

Filed:

Mar 31, 2000

Appl. No.:

09/541117

Inventors:

Hebbalalu S. Ramagopal - Austin TX
David B. Witt - Austin TX
Michael Allen - Austin TX
Moinul Syed - Austin TX
Ravi Kolagotla - Austin TX
William C. Anderson - Austin TX

Assignee:

Intel Corporation - Santa Clara CA
Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1200

US Classification:

711168, 711131, 711149, 711150, 711170

Abstract:

An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.

US Patent:

20200364152, Nov 19, 2020

Filed:

May 15, 2019

Appl. No.:

16/413034

Inventors:

- Suwon-si, KR
Moinul SYED - Austin TX, US
Ju-Hee CHOI - Seongnam-si, KR

Assignee:

Samsung Electronics Co., Ltd. - Suwon-si

International Classification:

G06F 12/1027
G06F 12/1009
G06F 12/0871

Abstract:

Memory management unit (MMU) in an application processor responds to an access request, corresponding to inspection request, including target context and target virtual address and the inspection request is for translating the target virtual address to a first target physical address. The MMU includes context cache, translation cache, invalidation queue and address translation manager (ATM). The context cache stores contexts and context identifiers of the stored contexts, while avoiding duplicating contexts. The translation cache stores first address and first context identifiers second addresses, the first address corresponds to virtual address, the first context identifiers corresponds to first context, and the second addresses corresponds to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated, of the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache and the invalidation queue.

US Patent:

20200257635, Aug 13, 2020

Filed:

Sep 5, 2019

Appl. No.:

16/562011

Inventors:

- Suwon-si, KR
MOINUL SYED - AUSTIN TX, US
JU-HEE CHOI - SEONGNAM-SI, KR

International Classification:

G06F 12/1009
G06F 12/0873

Abstract:

A processor includes a page table walk cache that stores address translation information, and a page table walker. The page table walker fetches first output addresses indicated by first indexes of a first input address by looking up the address translation information and at least a part of page tables, and compares a matching level between second indexes of a second input address and the first indexes of the first input address with a walk cache hit level obtained by looking up the page table walk cache using the second indexes.