Mohsen Alavi

US Patent:

6337507, Jan 8, 2002

Filed:

Dec 18, 1996

Appl. No.:

08/769152

Inventors:

Mark T. Bohr - Aloha OR
Mohsen Alavi - Beaverton OR
Min-Chun Tsai - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2900

US Classification:

257529, 438132

Abstract:

A fusible link device disposed on a semiconductor substrate for providing discretionary changes in resistance. The fusible link device of the invention includes a polysilicon layer having a first resistance. A silicide layer formed on the polysilicon layer has a second, lower resistance and includes a fuse region having a first notched region narrower than the center of the fuse region, a first contact region electrically coupled to one end of the fuse region and a second contact region electrically coupled to an opposite end of the fuse region. The silicide layer agglomerates to form an electrical discontinuity in the fuse region (usually in the notched region) in response to a current greater than or equal to a predetermined programming current flowing between the contact regions, such that the resistance of the fusible link device can be selectively increased.

US Patent:

6392271, May 21, 2002

Filed:

Jun 28, 1999

Appl. No.:

09/342022

Inventors:

Mohsen Alavi - Beaverton OR
Ebrahim Andideh - Portland OR
Scott Thompson - Portland OR
Mark T. Bohr - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2976

US Classification:

257328, 257331, 257365, 257329, 257302, 438176, 438173, 438178

Abstract:

A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer sited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

US Patent:

6624032, Sep 23, 2003

Filed:

Mar 20, 2002

Appl. No.:

10/102319

Inventors:

Mohsen Alavi - Beaverton OR
Ebrahim Andideh - Portland OR
Scott Thompson - Portland OR
Mark T. Bohr - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21336

US Classification:

438283, 438173, 438176, 438191, 438192, 438195, 438199, 438206, 438268, 438269, 438212, 438279, 257328, 257365, 257302

Abstract:

A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

US Patent:

6903598, Jun 7, 2005

Filed:

May 24, 2002

Appl. No.:

10/155512

Inventors:

Martin Spence Denham - Bend OR, US
Mohsen Alavi - Portland OR, US
Kaizad Rumy Mistry - Lake Oswego OR, US
Patrick John Ott - Hillsboro OR, US
Rachael Jade Parker - Forest Grove OR, US
Paul Gregory Slankard - Aloha OR, US
Wenliang Chen - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01H037/76
H01H085/00

US Classification:

327525

Abstract:

A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.

US Patent:

7102358, Sep 5, 2006

Filed:

Jun 29, 2004

Appl. No.:

10/880337

Inventors:

Ali Keshavarzi - Portland OR, US
Fabrice Paillet - Hillsboro OR, US
Muhammad M Khellah - Tigard OR, US
Dinesh Somasekhar - Portland OR, US
Yibin Ye - Portland OR, US
Stephen H Tang - Pleasanton CA, US
Mohsen Alavi - Portland OR, US
Vivek K De - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/26

US Classification:

324522, 324679

Abstract:

A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.

US Patent:

7102951, Sep 5, 2006

Filed:

Nov 1, 2004

Appl. No.:

10/979605

Inventors:

Fabrice Paillet - Hillsboro OR, US
Ali Keshavarzi - Portland OR, US
Muhammad M. Khellah - Tigard OR, US
Dinesh Somasekhar - Portland OR, US
Yibin Ye - Portland OR, US
Stephen H. Tang - Pleasanton CA, US
Mohsen Alavi - Portland OR, US
Vivek K. De - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 17/18

US Classification:

3652257, 365205

Abstract:

Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.

US Patent:

7110278, Sep 19, 2006

Filed:

Sep 29, 2004

Appl. No.:

10/954537

Inventors:

Ali Keshavarzi - Portland OR, US
Fabrice Paillet - Hillsboro OR, US
Muhammad M. Khellah - Lake Oswego OR, US
Dinesh Somasekhar - Portland OR, US
Yibin Ye - Portland OR, US
Stephen H. Tang - Beaverton OR, US
Mohsen Alavi - Portland OR, US
Vivek K. De - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 17/08

US Classification:

365104, 365 96, 365103, 327525, 257530

Abstract:

Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

US Patent:

7167397, Jan 23, 2007

Filed:

Jun 21, 2005

Appl. No.:

11/158518

Inventors:

Fabrice Paillet - Hillsboro OR, US
Ali Keshavarzi - Portland OR, US
Muhammad M. Khellah - Tigard OR, US
Dinesh Somasekhar - Portland OR, US
Yibin Ye - Portland OR, US
Stephen H. Tang - Pleasanton CA, US
Mohsen Alavi - Portland OR, US
Vivek K. De - Beaverton OR, US
Tanay Karnik - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 16/04

US Classification:

36518528, 36518523, 3652257

Abstract:

A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.