Michael L Shinkarovsky

US Patent:

60947357, Jul 25, 2000

Filed:

Aug 3, 1998

Appl. No.:

9/128041

Inventors:

Clifford B. Cole - Emmaus PA
Joseph D. Coyne - Lansdale PA
Bijit T. Patel - Breinigsville PA
Michael Shinkarovsky - Blue Bell PA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

G01R 3128

US Classification:

714724

Abstract:

An integrated circuit has digital logic that supports two or more different processing speeds and two or more different data rates that are distinguished by each data rate having a data prefix at a different common-mode voltage. For normal processing, the integrated circuit has one or more comparators that compare the average signal voltage level with one or more reference voltages to determine the data rate. According to one embodiment of the invention, one or more muxes are configured between the comparators and the digital logic. These muxes can be controlled during testing to by-pass the operations of the comparators to pass specified digital codes to the digital logic to simulate the operations of the comparators. In this way, the different processing speeds of the digital logic can be tested without having to build special automatic test equipment to support all of the different possible voltage levels corresponding to the different supported data rates.

US Patent:

52895807, Feb 22, 1994

Filed:

May 10, 1991

Appl. No.:

7/698585

Inventors:

Farrukh A. Latif - Malvern PA
Michael D. Stevens - Paoli PA
John A. Moysey - Malvern PA
Michael Shinkarovsky - Harleysville PA
Hung Nguyen - Downingtown PA
Michele Z. Dale - Audubon PA

Assignee:

Unisys Corporation - Plymouth Meeting PA

International Classification:

G06F 1300

US Classification:

395275

Abstract:

An I/O interface controller is disclosed which can be programmed to interact with a variety of interface protocols. The host side and the peripheral side of the interface controller are independently programmable. All significant operations are performed in a single chip gate array. The gate array includes registers for establishing control with peripheral devices and for transferring data between peripheral devices and the host. An arithmetic logic unit is used for calculation and data manipulation while an I/O operation is occurring. A condition code multiplexer evaluates the contents of registers within the single chip and instructs the sequencer to perform various operations based on these results. Strobe signals from a peripheral device, indicating that valid data is ready to be transferred, are quickly acknowledged by virtue of an asynchronous signal path. The strobe signal is also processed so that it may correspond with the internal clock of the I/O interface.