Michael L Larson

US Patent:

61674982, Dec 26, 2000

Filed:

Oct 2, 1997

Appl. No.:

8/944946

Inventors:

Michael Kerry Larson - Austin TX
Timothy James McDonald - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

G06F 1200

US Classification:

711202

Abstract:

A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325. The system CPU initiates data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the graphics engine 325. In an alternate embodiment, the subsystem includes a subsystem master control unit or MCU to enable parallel or simultaneous operation of the Host XY unit and the graphics subsystem MCU.

US Patent:

58414428, Nov 24, 1998

Filed:

Dec 30, 1996

Appl. No.:

8/777558

Inventors:

Mark Alan Einkauf - Leander TX
Michael Kerry Larson - Austin TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1500

US Classification:

345430

Abstract:

A method for computing input parameters used in a non-homogeneous second order perspective texture mapping process using interpolation. The present invention receives a polygon primitive (e. g. , triangle) including screen display coordinates and texture map coordinates for each vertex (vmin, vmid, and vmax). Based on vertex information including perspective weights, w, screen display coordinates and texture map coordinates are determined for midpoints (i and j) of the two triangle slopes opposite the triangle's major slope. Based on a determined quadratic equation of the triangle's major slope, screen coordinates and texture map coordinates are determined at several selected points (e. g. , imain, jmain, and midmain) along the major slope that corresponds to the i, j, and vmid points. From these values, quadratic coefficients a1, a2, and du. sub. -- ortho. sub.

US Patent:

57933863, Aug 11, 1998

Filed:

Jun 28, 1996

Appl. No.:

8/672620

Inventors:

Michael Kerry Larson - Austin TX
Patrick A. Harkin - Austin TX

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

G06F 1500

US Classification:

345522

Abstract:

A graphics system includes a graphics controller for rendering polygons with a minimum number of steps and registers. A host processor generates a display list that includes only the values necessary for rendering a primitive. The graphics controller includes a register file for receiving the display list either directly from the host processor or from system memory in which the host processor stored the display list. The graphics controller also includes logic to decode operational codes to ascertain which values from the register file must be used for rendering a primitive and which values can be skipped. Only the necessary values are transmitted to polygon and texture engines also included within the graphics processor.

US Patent:

5999200, Dec 7, 1999

Filed:

Jan 23, 1998

Appl. No.:

9/012333

Inventors:

Patrick A. Harkin - Austin TX
Michael K. Larson - Kirkland WA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1500

US Classification:

345522

Abstract:

A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes a command address feed logic device decodes the display list to determine the register locations in a register file to fill with data. The command address feed logic device decodes the display list and orders a group of registers in the register file in order to perform a sequential write to the register file. By sequentially ordering the register file locations, the command address feed logic device is able to write null or zero data values to the register locations which are not needed to render a primitive, while maintaining a single write cycle to the register file.

US Patent:

58350977, Nov 10, 1998

Filed:

Dec 30, 1996

Appl. No.:

8/774787

Inventors:

Gautam P. Vaswani - Austin TX
Michael Larson - Austin TX
Tom Dye - Austin TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1500

US Classification:

345430

Abstract:

In a computer system having a host processor, a peripheral graphics device, a display screen, and a memory, a non-homogenous second order perspective texture mapping process. Polygon coordinates, a. sub. m,n, defining a texture polygon, are received. Initial values are received for a set of parameters including u. sub. main, v. sub. main, dv. sub. ortho, dv. sub. main, du. sub. ortho, du. sub. main, d. sup. 2 u. sub. ortho, d. sup. 2 u. sub. main, d. sup. 2 v. sub. ortho, d. sup. 2 v. sub. main, du. sub. ortho-ADD, and dv. sub. ortho-ADD. The texture polygon includes span regions. A span value, j, is set to an initial value to designate an initial span region of the texture polygon in (m, n) polygon coordinate space. The total number of rows, n. sub. max, is determined for the current span region of the polygon.

US Patent:

60880465, Jul 11, 2000

Filed:

Oct 2, 1997

Appl. No.:

8/942779

Inventors:

Michael Kerry Larson - Austin TX
Timothy James McDonald - Austin TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1576

US Classification:

345516

Abstract:

A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325, a host interface bus 301 and a host interface bus master circuit 321 for initiating data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit 327, 317 processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit 327, 317 to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the requesting graphics engine 325.

US Patent:

60521279, Apr 18, 2000

Filed:

Dec 30, 1996

Appl. No.:

8/777556

Inventors:

Gautam P. Vaswani - Austin TX
Michael K. Larson - Austin TX
Tom A. Dye - Austin TX
Daniel Wilde - Cedar Park TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1500

US Classification:

345430

Abstract:

A texture value determining (TVD) circuit approximates non-homogenous 2nd order perspective texture mapping to provide texture for a polygon using linear interpolation and input parameters. The TVD circuit of the present invention includes a vertical walk subcircuit and an orthogonal walk subcircuit. The vertical walk subcircuit determines texture coordinates, u(a. sub. 0,n) and v(a. sub. 0,n) that represent the pixels along a vertical main slop of a triangle polygon. The orthogonal walk subcircuit determines texture coordinates, u(a. sub. m,n) and v(a. sub. m,n), for orthogonally walked polygon coordinate positions for which m>0. The orthogonally walked coordinate positions represent individual scan lines. The vertical walk subcircuit of the TVD circuit includes adders, latches, and accumulators. Each element of the vertical walk subcircuit receives a vertical main slope clock (n-clock) signal.

US Patent:

59175052, Jun 29, 1999

Filed:

Dec 19, 1995

Appl. No.:

8/574835

Inventors:

Michael L. Larson - Austin TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1500
G06T 100

US Classification:

345522

Abstract:

A graphics processor for rasterizing graphics data using display list programming to a host computer system memory. The processor dynamically rasterizes the display list generated by a host processor to either graphics memory local to the graphics processor or to the host system memory. The graphics processor of the present invention includes a prefetch unit having instruction prefetch logic for prefetching and decoding next opcode instructions in a display list of instructions from system memory. Prefetching a next instruction eliminates steup time necessary to fetch subsequent opcode instructions after a first opcode instruction has been fetched. The next opcode instruction in a sequential display list of instructions is prefetched with parameter data associated with the first fetched opcode instructions to save the graphics processor extra instruction fetch cycle time necessary to fetch subsequent opcode instructions. The graphics processor further includes a bus mastering unit which allows the graphics processor to master the host computer system bus during the transfer of display list instructions from host computer system memory and the subsequent processing of these instructions in an uninterrupted mode.

Author:

Michael Larson

ISBN #:

0595390048

Author:

Michael Larson

ISBN #:

0595393241

Author:

Michael Larson

ISBN #:

0595834175

Author:

Michael Larson

ISBN #:

0789725150

Author:

Michael L. Larson

ISBN #:

0595676944

Author:

Michael L. Larson

ISBN #:

0595677258

Author:

Michael C. Larson

ISBN #:

0208024743