Melvy F Miller from Parks, AZ, age 70

Us Patents

Method Of Making A Semiconductor Device, And Semiconductor Device Made Thereby
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US Patent:

6919244, Jul 19, 2005
Filed:

Mar 10, 2004
Appl. No.:

10/799554
Inventors:

Thomas P. Remmel - Mesa AZ, US
Sriram Kalpat - Austin TX, US
Melvy F. Miller - Tempe AZ, US
Peter Zurcher - Phoenix AZ, US
Assignee:

Motorola, Inc. - Schaumburg IL
International Classification:

H01L021/8242
US Classification:

438239, 438253, 438396
Abstract:

A method of making a semiconductor device includes the steps of: providing a semiconductor substrate () having a patterned interconnect layer () formed thereon; depositing a first dielectric material () over the interconnect layer; depositing a first electrode material () over the first dielectric material; depositing a second dielectric material () over the first electrode material; depositing a second electrode material () over the second dielectric material; patterning the second electrode material to form a top electrode () of a first capacitor (); and patterning the first electrode material to form a top electrode () of a second capacitor (), to form an electrode () of the first capacitor, and to define a resistor ().

Method Of Manufacturing A Passive Integrated Matching Network For Power Amplifiers
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US Patent:

7276420, Oct 2, 2007
Filed:

Jul 11, 2005
Appl. No.:

11/179685
Inventors:

Lianjun Liu - Gilbert AZ, US
Qiang Li - Gilbert AZ, US
Melvy F. Miller - Tempe AZ, US
Sergio P. Pacheco - Phoenix AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 21/338
H01L 21/337
H01L 21/8222
H01L 21/20
US Classification:

438329, 438171, 438190, 438210, 438393
Abstract:

An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Method Of Making A Semiconductor Device, And Semiconductor Device Made Thereby
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US Patent:

7306986, Dec 11, 2007
Filed:

Jun 9, 2005
Appl. No.:

11/150499
Inventors:

Thomas P. Remmel - Mesa AZ, US
Sriram Kalpat - Austin TX, US
Melvy F. Miller - Tempe AZ, US
Peter Zurcher - Phoenix AZ, US
Assignee:

Freescale Semiconductor, Inc. - Schaumburg IL
International Classification:

H01L 21/8242
US Classification:

438239, 438253, 438381, 438396, 257E21647
Abstract:

A method of making a semiconductor device includes the steps of: providing a semiconductor substrate () having a patterned interconnect layer () formed thereon; depositing a first dielectric material () over the interconnect layer; depositing a first electrode material () over the first dielectric material; depositing a second dielectric material () over the first electrode material; depositing a second electrode material () over the second dielectric material; patterning the second electrode material to form a top electrode () of a first capacitor (); and patterning the first electrode material to form atop electrode () of a second capacitor (), to form an electrode () of the first capacitor, and to define a resistor ().

Method For Manufacturing A Passive Integrated Matching Network For Power Amplifiers
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US Patent:

7439606, Oct 21, 2008
Filed:

Jul 30, 2007
Appl. No.:

11/830577
Inventors:

Lianjun Liu - Gilbert AZ, US
Qiang Li - Gilbert AZ, US
Melvy F. Miller - Tempe AZ, US
Sergio P. Pacheco - Phoenix AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 29/00
US Classification:

257528, 257531, 257532
Abstract:

An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Integrated Matching Network And Method For Manufacturing Integrated Matching Networks
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US Patent:

7528062, May 5, 2009
Filed:

Oct 25, 2006
Appl. No.:

11/586807
Inventors:

Melvy F. Miller - Tempe AZ, US
Juergen A. Foerstner - Mesa AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 21/44
H01L 23/52
US Classification:

438614, 257777
Abstract:

An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming () a first die on a substrate, forming () a second die on the substrate, and forming () a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a PA (), a second die having a capacitor (), and a metal interconnect () coupled to the PA and the first capacitor. The metal interconnect () has an inductance. The capacitor () and metal interconnect () form a shunt impedance.

Semiconductor Device Comprising Passive Components
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US Patent:

7535079, May 19, 2009
Filed:

Sep 4, 2007
Appl. No.:

11/899218
Inventors:

Thomas P. Remmel - Mesa AZ, US
Sriram Kalpat - Austin TX, US
Melvy F. Miller - Tempe AZ, US
Peter Zurcher - Phoenix AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 29/00
US Classification:

257532, 257533, 257E29343
Abstract:

A method of making a semiconductor device includes the steps of: providing a semiconductor substrate () having a patterned interconnect layer () formed thereon; depositing a first dielectric material () over the interconnect layer; depositing a first electrode material () over the first dielectric material; depositing a second dielectric material () over the first electrode material; depositing a second electrode material () over the second dielectric material; patterning the second electrode material to form a top electrode () of a first capacitor (); and patterning the first electrode material to form a top electrode () of a second capacitor (), to form an electrode () of the first capacitor, and to define a resistor ().

Re-Configurable Impedance Matching And Harmonic Filter System
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US Patent:

7567782, Jul 28, 2009
Filed:

Jul 28, 2006
Appl. No.:

11/494821
Inventors:

Lianjun Liu - Chandler AZ, US
Melvy F. Miller - Tempe AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H04B 1/04
US Classification:

455121, 455129, 455102, 4551141
Abstract:

Methods and apparatus are provided to enable a transceiver () or transmitter including a single PA line-up () to transmit signals having frequencies in two or more different frequency bands, and/or having two or more different modulation types, and/or having two or more different RF power levels. The single PA line-up includes at least one variable matching circuit () and a variable harmonic filter () to tune match and tune filter communication signals prior to transmission. The variable matching circuit and the variable harmonic filter each include at least one variable capacitive element ( and ) that switches ON/OFF depending on whether a low frequency signal or a high frequency signal is being transmitted. Each variable capacitive element includes separate direct current and radio frequency terminals to enable the single PA line-up to change signal modulation and/or RF power levels in addition to frequencies.

Integrated Passive Device And Method Of Fabrication
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US Patent:

7663196, Feb 16, 2010
Filed:

Feb 9, 2007
Appl. No.:

11/673015
Inventors:

Lianjun Liu - Chandler AZ, US
Melvy F. Miller - Tempe AZ, US
Assignee:

Freescale Semiconductor, Inc. - Austin TX
International Classification:

H01L 27/14
H01L 29/82
H01L 29/84
H01L 29/00
US Classification:

257416, 257414, 257533, 257E27025, 257E29324, 257E31113
Abstract:

A device includes substrates and coupled to form a volume between the substrates. A surface of the substrate faces a surface of the substrate. A metal-insulator-metal capacitor is formed on one of the surfaces and. A conductive element spans between a top electrode of the capacitor and the other surface and. Vias and extend through the substrate and are electrically interconnected with the conductive element and a bottom electrode of the capacitor. Another device includes an underpass transmission line formed on a surface of a substrate within a volume formed between the substrate and another substrate. The line underlies an integrated device formed on a surface of the substrate.